The high dissipation across the series-pass transistor in a linear regu- lator and the large 60-Hz transformer required for line operation made linear regulators unattractive for modern electronic applications.
Further, the high power loss in the series device requires a large heat sink and large storage capacitors and makes the linear power supply disproportionately large.
As electronics advanced, integrated circuits made the electronic sys- tems smaller. Typically, linear regulators could achieve output power densities of 0.2 to 0.3 W/in3, and this was not good enough for the ever smaller modern electronic systems. Further, linear power sup- plies could not provide the extended hold-up time required for the controlled shutdown of digital storage systems.
Although the technology was previously well known, switching regulators started being widely used as alternatives to linear reg- ulators only in the early 1960s when suitable semiconductors with reasonable performance and cost became available. Typically these new switching supplies used a transistor switch to generate a square- waveform from a non-regulated DC input voltage. This square wave, with adjustable duty cycle, was applied to a low pass output power filter so as to provide a regulated DC output.
Usually the filter would be an inductor (or more correctly a choke, since it had to support some DC) and an output capacitor. By varying the duty cycle, the average DC voltage developed across the output capacitor could be controlled. The low pass filter ensured that the DC output voltage would be the average value of the rectangular voltage pulses (of adjustable duty cycle) as applied to the input of the low pass filter. A typical topology and waveforms are shown later in Figure 1.4.
With appropriately chosen low pass inductor/capacitor (LC) fil- ters, the square-wave modulation could be effectively minimized, and near-ripple-free DC output voltages, equal to the average value of the duty-cycle-modulated raw DC input, could be provided. By sens- ing the DC output voltage and controlling the switch duty cycle in a negative-feedback loop, the DC output could be regulated against input line voltage changes and output load changes.
Modern very high frequency switching supplies are currently achieving up to 20 W/in3compared with 0.3 W/in3for the older linear power supplies. Further, they are capable of generating a multiplicity of isolated output voltages from a single input. They do not require a 50/60-Hz isolation power transformer, and they have efficiencies from 70% up to 95%. Some DC/DC converter designers are claiming load power densities of up to 50 W/in3for the actual switching elements.
1.3.1.1 Basic Elements and Waveforms of a Typical Buck Regulator After Pressman In the interest of simplicity, Mr. Pressman describes fixed-frequency operation for the following switching regulator examples. In such regulators theonperiod of the power device (Ton) is adjusted to maintain
FIGURE1.4 Buck switching regulator and typical waveforms.
regulation, while the total cycle period (T) is fixed, and the frequency is thus fixed at 1/T.
The ratioTon/Tis normally referred to as theduty ratioorduty cycle (D) in many modern treatises. In other books on the subject, you may find this shown asTon/(Ton+Toff), whereToffis theoffperiod of the power device so thatTon+Toff=T.OperatorsDandMare also used in various combinations but essentially refer to the same quantity.
Bear in mind that other modes of operation can be and are used. For exam- ple, theonperiod can be fixed and the frequency changed, or a combination of both may be employed.
The termsdI, di, dV, dv, dTanddtare used somewhat loosely in this book and normally refer to the changesI,V,andt,where, for example, in the
limit,I/tgoes to the derivativedi/dt,giving the rate of change of current with time or the slope of the waveform. Since in most cases the waveform slopes are linear the result is the same so this becomes a moot point.∼K.B.
1.3.1.2 Buck Regulator Basic Operation
The basic elements of the buck regulator are shown in Figure 1.4.
TransistorQ1 is switched hard “on” and hard “off” in series with the DC inputVdcto produce a rectangular voltage at pointV1. For fixed- frequency duty-cycle control,Q1 conducts for a timeTon(a small part of the total switching periodT).WhenQ1 is “on,” the voltage atV1 is Vdc, assuming for the moment the “on” voltage drop acrossQ1 is zero.
A current builds up in the series inductorLoflowing toward the out- put. WhenQ1 turns “off,” the voltage atV1 is driven rapidly toward ground by the current flowing in inductorLoand will go negative un- til it is caught and clamped at about−0.8 V by diodeD1 (the so-called free-wheeling diode).
Assume for the moment that the “on” drop of diodeD1 is zero. The square voltage shown in Figure 1.4bwould be rectangular, ranging betweenVdcand ground, (0 V) with a “high” period ofTon. The average value of this rectangular waveform isVdcTon/T.The low passLoCo filter in series betweenV1 and the outputVextracts the DC component and yields a clean, near-ripple-free DC voltage at the output with a magnitudeVoofVdcTon/T.
To control the voltage,Vois sensed by sampling resistorsR1 andR2 and compared with a reference voltageVrefin the error amplifier (EA).
The amplified DC error voltageVeais fed to a pulse-width-modulator (PWM). In this example the PWM is essentially a voltage compara- tor with a sawtooth waveform as the other input (see Figure 1.4a).
This sawtooth waveform has a periodT and amplitude typically in the order of 3 V. The high-gain PWM voltage comparator generates a rectangular output waveform (Vwm, see Figure 1.4c) that goes high at the start of the sawtooth ramp, and goes low the instant the ramp volt- age crosses the DC voltage level from the error-amplifier output. The PWM output pulse width (Ton) is thus controlled by the EA amplifier output voltage.
The PWM output pulse is fed to a driver circuit and used to control the “on” time of transistor switch Q1 inside the negative-feedback loop. The phasing is such that ifVdcgoes slightly higher, the EA DC level goes closer to the bottom of the ramp, the ramp crosses the EA output level earlier, and theQ1 “on” time decreases, maintaining the output voltage constant. Similarly, ifVdcis reduced, the “on” time of Q1 increases to maintainVoconstant. In general, for all changes, the
“on” time of Q1 is controlled so as to make the sampled DC output voltageVoR2/(R1+R2) closely track the reference voltageVref.