After Pressman The switching loss is much more difficult to establish, because it depends on many variables relating to the performance of the semiconductors and to the methods of driving the switching devices. Other variables, related to the actual power circuit designs, include the action of any
snubbers, load line shaping, and energy recovery arrangements. It depends on what the designer may choose to use in a particular design. (See Chapter 11.) Unless all these things are considered, any calculations are at best only a very rough approximation and can be far from the real values found in the actual design, particularly at high frequencies with the very fast switching devices now available.
After Pressman I leave Mr. Pressman’s original calculations, shown next, untouched except for some minor editing, because they serve to il- lustrate the root cause of the switching loss. However, I would recommend that the reader consider using more practical methods to establish the real loss. Many semiconductor manufacturers now provide switching loss equa- tions for their switching devices when recommended drive conditions are used, particularly the modern fastIGBTs(Insulated Gate Bipolar Transis- tors). Some fast digital oscilloscopes claim that they will actually measure switching loss, providing the real-time device current and voltage is accu- rately provided to the oscilloscope. (Doing this can also be problematical at very high frequency.)
The method I prefer, which is unquestionably accurate, is to measure the temperature rise of the device in question in a working model. The model must include all the intended snubbers and load line shaping circuits, etc.
Replacing the AC current in the device with a DC current to obtain the same temperature rise will provide a direct indication of power loss by simple DC power measurements. This method also allows easy optimization of the drive and load line shaping, which can be dynamically adjusted during operation for minimum temperature rise and hence minimum switching loss.∼K.B.
Mr. Pressman continues as follows:
Alternating-current switching loss (or voltage/current overlap loss) calculation depends on the shape and timing of the rising and falling voltage and current waveforms. An idealized linear example—which is unlikely to exist in practice—is shown in Figure 1.5a and serves to illustrate the principle.
Figure 1.5a shows the best-case scenario. At the turn “on” of the switching device, the voltage and current start changing simulta- neously and reach their final values simultaneously. The current waveform goes from 0 toIo,and voltage acrossQ1 goes from a max- imum ofVdcdown to zero. The average power during this switching transition isP(Ton)=Ton
0 IV dt= IoVdc/6, and the power averaged over one complete period is (IoVdc/6)(Ton/T).
Assuming the same scenario of simultaneous starting and ending points for the current fall and voltage rise waveforms at the turn “off”
transition, the voltage/current overlap dissipation at this transition is given byP(Toff) =Toff
0 IV dt = IoVdc/6 and this power averaged over one complete cycle is (IoVdc/6)(Toff/T).
FIGURE1.5 Idealized transistor switching waveforms. (a) Waveforms show the voltage and current transitions starting and ending simultaneously.
(b) Waveforms show the worst-case scenario, where at turn “on” voltage remains constant atVdc(max)until current reaches its maximum. At turn “off,”
the current remains constant atIountilQ1 voltage reaches its maximum ofVdc.
AssumingTon = Toff = Ts, the total switching losses (the sum of turn “off” and turn “on” losses) arePac=(VdcIoTs)/3T,and efficiency is calculated as shown next in Eq. 1.4.
Efficiency= Po
Po+DC losses+AC losses
= VoIo
VoIo+1Io+VdcIoTs/3T (1.4)
= Vo
Vo+1+VdcTs/3T
It would make an interesting comparison to calculate the efficiency of the buck regulator and compare it with that of a linear regulator.
Assume the buck regulator provides 5 V from a 48-V DC input at 50-kHz switching frequency (T= 20μs).
If there were no AC switching losses and a switching transition period Ts of 0.3μs were assumed, Eq. 1.3 would give a conduction loss efficiency of
Efficiency = 5
5+1 =83.3%
If switching losses for the best-case scenario as shown in Figure 1.5a were assumed, forTs = 0.3μs andT =20μs, Eq. 1.4 would give a switching-related efficiency of
Efficiency = 5
5+1+48×0.3/3×20
= 5
5+1+0.24= 5 5+1.24
=80.1%
If a worst-case scenario were assumed (which is closer to reality), as shown in Figure 1.5b, efficiencies would lower. In Figure 1.5bit is assumed that at turn “on” the voltage across the transistor remains at its maximum value (Vdc) until the on-turning current reaches its maximum value ofIo.Then the voltage starts falling. To a close ap- proximation, the current rise timeTcrwill equal voltage fall time. Then the turn “on” switching losses will be
P(Ton)= VdeIo 2
Tcr
T + IoVdc 2
Tvf T also forTcr=Tvf=Ts,P(Ton)=VdcIo(Ts/T).
At turn “off” (as seen in Figure 1.5b), we may assume that current hangs on at this maximum valueIo until the voltage has risen to its maximum value ofVdcin a timeTvr. Then current starts falling and reaches zero in a timeTcf. The total turn “off” dissipation will be
P(Toff)= IoVdc 2
Tvr
T + VdcIo 2
Tcf T
WithTvr=Tcf=Ts,P(Toff)=VdcIo(Ts/T). The total AC losses (the sum of the turn “on” plus the turn “off” losses) will be
Pac=2VdcIoTs
T (1.5)
and the total losses (the sum of DC plus AC losses) will be Pt =Pdc+Pac=1Io+2VdcIoTs
T (1.6)
and the efficiency will be Efficiency = Po
Po+Pt = VoIo
VoIo+1Io+2VdcIoTs/T
= Vo
Vo+1+2VdcTs/T (1.7)
Hence in the worst-case scenario, for the same buck regulator with Ts=0.3μs, the efficiency from Eq. 1.7 will be
Efficiency = 5
5+1+2×48×0.3/20 = 5 5+1+1.44
= 5
5+1+2.44
=67.2%
Comparing this with a linear regulator doing the same job (bringing 48 V down to 5 V), its efficiency (from Eq. 1.1) would beVo/Vdc(max), or 5/48; this is only 10.4% and is clearly unacceptable.