4.10.1 Area of Application
The topology is shown in Figure 4.8a. Its major advantage is that, using the scheme of the double-ended forward converter of Figure 2.13, its power transistors in the “off” state are subjected to only the maximum DC input voltage. This is a significant advantage over the single-ended forward converter of Figure 4.1, where the maximum “off”-voltage stress is the maximum DC input voltage plus the reflected secondary voltage (Np/Ns)(Vo+1) plus a leakage inductance spike that may be as high as one-third of the DC input voltage.
4.10.2 Basic Operation
The lower “off”-voltage stress comes about in the same way as for the double-ended forward converter of Figure 2.13. Power transis- torsQ1,Q2 are turned “on” simultaneously. When they are “on,” the dot end of the secondary is negative, D3 is reverse-biased, and no secondary current flows. The primary is then just an inductor, and current in it ramps up linearly at a rate ofdI1/dt = Vdc/(Lm+Ll), where Lm and Ll are the primary magnetizing and leakage induc- tances, respectively. When Q1 andQ2 turn “off,” as in the previous flybacks, all primary and secondary voltages reverse polarity,D3 be- comes forward-biased, and the stored energy in Lm =1/2Lm(I1)2is delivered to the load.
As shown previously, the “on” or set volt-second product across the primary must equal the “off” or reset volt-second product. At the instant of turn “off,” the bottom end ofLlattempts to go far positive but is clamped to the positive end ofVdc. The top end ofLmattempts to go far negative but is clamped to the negative end of Vdc. Thus the maximum voltage stress at either Q1 or Q2 can never be more thanVdc.
The actual resetting voltageVr across the magnetizing inductance Lm during the “off” time is given by the voltage reflected from the secondary (Np/Ns)(Vo+VD3). The voltage acrossLmandLlin series is the DC supply voltage, and hence, as seen in Figure 4.8b, the voltage across the leakage inductanceLlisVl=(Vdc−Vr).
The division of theVdcsupply voltage acrossLm andLl in series during the “off” time is a very important point in the circuit design and establishes the transformer turns ratioNp/Nsas discussed below.
The price paid for this advantage is, of course, the requirement for two transistors and the two clamp diodes,D1,D2.
FIGURE4.8 Circuit duringQ1 andQ2 “off” time. CurrentI1, stored inLm
duringQ1,Q2 “on” time, also flows through leakage inductanceLl. During the “off” time, energy stored inLmmust be delivered to the secondary load as reflected into the primary acrossLm. ButI1also flows throughLl, and during the “off” time, the energy it represents (1/2LlI2) is returned to the input sourceVdcthrough diodesD1,D2. This robs energy that should have been delivered to the output load and continues to rob energy untilI1, the leakage inductance current, falls to zero. To minimize the time forI1inLlto fall to zero,Viis made significantly large by keeping the reflected voltage Vr(=Np/Ns)(Vo+VD3) low by setting a lowNp/Nsturns ratio. A usual value forVris two-thirds of the minimumVdc, leaving one-third forVl.
4.10.3 Leakage Inductance Effect in Double-Ended Flyback
Figure 4.8bshows the circuit during theQ1,Q2 “off” time. The voltage acrossLmandLl in series is clamped toVdcthrough diodes D1,D2 The voltageVr across the magnetizing inductance is clamped against the reflected secondary voltage and equals (Np/Ns)(Vo+VD3). The voltage acrossLlis thenVl =Vdc−Vr.
At the instant of turn “off,” the same current I1 flows in Lmand Ll(I3 = I1at instant of turn “off”). That current inLlflows through diodesD1,D2 and returns its stored energy to the supply sourceVdc. TheLlcurrent decays at a rate ofdI1/dt= Vl/Ll as shown in Figure 4.9a as slopeACorAD. The current inLm (initially also equal toI1) decays at a rateVr/Lmand is shown in Figure 4.9aas slopeAB.
The current actually delivering power to the load isI2—the differ- ence between the currents inLmandLl. This is shown as currentRST in Figure 4.9bif theL1current slope isACof Figure 4.9a.The larger area currentUVWin Figure 4.9cresults if theL1current slope is faster, asADof Figure 4.9a.It should be evident in Figures 4.9band 4.9cthat so long as current still flows in leakage inductanceLl, throughD1 and D2 back into the supply source, all the current available inLmdoes
FIGURE4.9 (a) Currents in magnetizing and leakage inductances in double-ended flyback. (b) Current into reflected load impedance for large Np/Nsratio.AB–ACof Figure 4.9a.(c) Current into reflected load impedance for smallerNp/Nsratio.AB–ADof Figure 4.9a.
not flow into the reflected load but is partly diverted back into the supply.
It can thus be seen from Figures 4.9band 4.9cthat to maximize the transfer ofLmcurrent to the reflected load and to avoid a delay in the transfer of current to the load, the slope of the leakage inductance cur- rent decay should be maximized (slopeADrather thanACin Figure 4.9a). Or in magnetics–power supply jargon, the leakage inductance current should be rapidly reset to zero.
Since the rate of decay of the leakage inductance current isVl/Ll
andVl = Vdc−(Np/Ns)(Vo+VD3), choosing lower values ofNp/Ns
increasesVl and hastens leakage current reset. A usual value for the reflected voltage (Np/Ns)(Vo+VD3) is two-thirds ofVdc, leaving one- third forVl. Too low a value forVr will require a longer time to reset the magnetizing inductance, rob from the availableQ1,Q2 “on” time, and decrease the available output power.
Once Np/Ns has been fixed to yield Vl = Vdc/3, the maximum
“on” time for discontinuous operation is calculated from Eq. 4.7,Lm is calculated from Eq. 4.8 andIpfrom Eq. 4.9, just as for the single- ended flyback.
References
1. Billings, K.,Switchmode Power Supply Handbook,McGraw-Hill, New York, 1989.
2. Chryssis, G.,High Frequency Switching Power Supplies,2nd Ed., McGraw-Hill, New York, 1989, pp. 122–131.
3. Dixon, L., “The Effects of Leakage Inductance on Multi-output Flyback Circuits,” Unitrode Power Supply Design Seminar Handbook,Unitrode Corp., Lexington, Mass., 1988.
4. Patel, R., D. Reilly, and R. Adair, “150 Watt Flyback Regulator,”Unitrode Power Supply Design Seminar Handbook,Unitrode Corp., Lexington, Mass., 1988.
C H A P T E R 5
Current-Mode and Current-Fed Topologies