17.1 Integral and technological functions
17.1.1 High-speed counter (HSC)
Contrary to a counter function, a high-speed counter (HSC) counts pulses inde- pendent of the cycle time of the user program. A counting frequency up to 200 kHz is possible. The counting range corresponds to the range of values of a DINT tag (–2 147 483 648 to +2 147 483 647).
A high-speed counter is an integral component of the CPU and must be activated and configured prior to use. The number of available high-speed counters depends on the CPU: three counters for the CPU 1211, four counter for the CPU 1212, and six counters for the CPU 1214 and CPU 1215. The number of high-speed counters with the CPU 1211 and CPU 1212 can be increased by using a signal board with digital input channels.
A high-speed counter can be used as a single-phase or two-phase counter (A/B quadrature). Please note that – depending on the operating mode – specific input channels are permanently assigned to a high-speed counter and that this may re- sult in limitations when using the counter. The assignment of the counter inputs af- fects the peripheral inputs (the input terminals). A change in the (logical) input ad- dresses has no influence on this assignment.
With correspondingly designed signal boards, the maximum counting frequency of 100 kHz achievable with the onboard inputs of the CPU can be increased to 200 kHz.
The data required for execution of a counter function is saved in a data block. When calling the counter function as a single instance, this is a separate data block per call, when calling as a local instance in a function block, the instance data block of the function block can be used for data saving (multi-instance).
Assignment of inputs to high-speed counters
Depending on the operating mode, specific inputs integrated on the CPU or on the signal board are assigned to a high-speed counter (Table 17.1). If a counter uses the inputs, they cannot be used elsewhere. Unused inputs can be used like “normal”
inputs for other purposes. Inputs used by a high-speed counter cannot be forced (assigned a fixed value).
As the table shows, the assignable inputs of HSC 1 and HSC 2 (I 0.1, I 0.3) as well as of HSC 3 and HSC 4 (I 0.5, I 0.7) overlap, meaning that not all counters can be used in every mode. If both counters are to be used in each case, it is possible to change
back to the inputs of the signal board or adapt the operating modes. For example, control of the counting direction and resetting can also be carried out with the CTRL_HSC statement as an alternative to the external inputs.
Fig. 17.1 shows which inputs and outputs are used by a high-speed counter depend- ing on the operating mode.
Table 17.1 Assignment of onboard inputs to counters (without signal board) CPU input HSC No. For single-phase
counter mode
For two-phase counter mode
For A/B quadrature mode
I 0.0 HSC 1 Clock input Clock input up Clock phase A
I 0.1 HSC 1
HSC 2
Direction Reset
Clock input down Reset
Clock phase B Clock phase Z
I 0.2 HSC 2 Clock input Clock input up Clock phase A
I 0.3 HSC 1
HSC 2 Reset Direction
Reset
Clock input down
Clock phase Z Clock phase B
I 0.4 HSC 3 Clock input Clock input up Clock phase A
I 0.5 HSC 3
HSC 4
Direction Reset
Clock input down Reset
Clock phase B Clock phase Z
I 0.6 HSC 4 Clock input Clock input up Clock phase A
I 0.7 HSC 3
HSC 4 Reset Direction
Reset
Clock input down
Clock phase Z Clock phase B
I 1.0 HSC 5 Clock input Clock input up Clock phase A
I 1.1 HSC 5 Direction Clock input down Clock phase B
I 1.2 HSC 5 Reset Reset Clock phase Z
I 1.3 HSC 6 Clock input Clock input up Clock phase A
I 1.4 HSC 6 Direction Clock input down Clock phase B
I 1.5 HSC 6 Reset Reset Clock phase Z
Fig. 17.1 Inputs and outputs of a high-speed counter Single-phase counter
Two-phase counter, A/B quadrature Clock input
Reset Direction Reset
Clock input 1 Clock input 2
Actual count value = reference value Change in counting direction External reset Actual count value Inputs and outputs of a high-speed counter (HSC)
Pulse train
Pulse train 1 or phase A
In the peripheral input area Process interrupt event
Process interrupt event
Process interrupt event
Alternatively: external counting direction control
Pulse train 2 or phase B Optional: external setting to the initial count value
Optional: external setting to the initial count value
Operating modes of a high-speed counter
Fig. 17.2 shows the possible counting modes of a high-speed counter.
Single-phase counter: the counter is controlled by a single pulse train. The counting direction is specified either internally with the CTRL_HSC statement or externally via an input. Each rising edge of a pulse increases or decreases the count value de- pending on the actual counting direction.
Two-phase counter: The counter is controlled by two independent pulse trains, one for the up counting direction and one for the down counting direction. Each rising edge of a pulse increases or decreases the count value depending on the pulse train.
Please note that with the first pulse of the other input in each case, there is a change in the counting direction and therefore – if activated – the associated process inter- rupt will be triggered.
A/B quadrature with single speed: The counter is controlled by two pulse trains offset by 90° (“Phase A” and “Phase B”). If the pulse train of phase B has signal state “0”
(“between” the pulses), counting is enabled: then each rising edge of the pulses of phase A results in an increase in the count value, and each falling edge a decrease.
A/B counter with quadruple speed:The counter is controlled by two pulse trains off- set by 90° (“Phase A” and “Phase B”). Each edge of each pulse train is counted.
Fig. 17.2 Operating modes of a high-speed counter Operating modes of a high-speed counter (HSC)
Single-phase counter
Two-phase counter
A/B quadrature (1x)
A/B quadrature (4x) Clock input
Clock input up
Clock phase A
Clock phase A Clock input down
Clock phase B
Clock phase B
Counts one pulse with counting direction up
Counts one pulse with counting direction down
Counts one pulse with the set counting direction
Functional principle of a high-speed counter
A high-speed counter can be operated with three counting modes: counting, frequency meter or motion axis.
Pulses are counted in the Counting mode, either from one or two pulse trains de- pending on the operating mode. With only one pulse train for the counter input, the counting direction is controlled either internally or externally by an input. The initial count value and a reference value can be defined. The count value can be re- set to the initial value via an input or per program. A fast counter in Counting mode delivers the actual count value as well as interrupt events if the actual count value is equal to the reference value, if the counting direction is changed, and if the counter is reset externally.
The number of changes in the count value per time interval is counted in the Frequency mode. The frequency value output is a mean value over the time interval.
With only one pulse train for the counter input, the counting direction is controlled either internally or externally by an input. The measuring period (the time interval) can be defined. A fast counter in Frequency mode delivers the mean value of the fre- quency over the measured period as well as interrupt events if the actual count val- ue is equal to the reference value, if the counting direction is changed, and if the counter is reset externally.
In the Motion axis mode, the high-speed counter is used by the technological object Axis and therefore cannot be used for other purposes (applies to counters HSC 1 and HSC 2).
Actual count value
The current count value is not made available as a block parameter at the counter box, but is stored by the counter in the process image input (Table 17.2). Note, however, that the actual count value is no longer up-to-date when it is read and processed by the user program if the counter is counting at high speed.
A comparison between the actual count value and a “target value” can be carried out indirectly by loading the “target value” as a reference value and – when the “tar- get value” has been reached – evaluating the attainment of the “target value” in the interrupt routine (react accordingly) and loading a new reference value (the next
“target value”).
The mean value of the frequency is output in Hertz (changes per second) in the Frequency mode, independent of the time interval of the measuring period.
Table 17.2 Memory addresses for the current count values of the high-speed counters High-speed counter
HSC
1 2 3 4 5 6
Current count value in %ID1000 %ID1004 %ID1008 %ID1012 %ID1016 %ID1020
Configuring a high-speed counter
A high-speed counter must be activated using the hardware configuration editor.
In order to configure a high-speed counter, start the Device configuration editor un- der the PLC station in the project tree. Select a high-speed counter in the properties of the CPU module in the inspector window, and activate it using the Enable this high-speed counter for use check box.
You set the counting mode (counting, frequency, or axis of motion) under Func- tion and under Operating phase you set the manner in which the count pulses are to be made available and counted (single-phase, two-phase, A/B counter 1X, A/B counter 4X). If a signal board is plugged in, you can select the input source (inte- grated CPU input, signal board input) for the HSC 1, HSC 2, HSC 5, and HSC 6 counters. The inputs of a counter (counter input, direction input, reset input) are either all on the CPU or all on the signal board. If you have selected Single-phase for the operating phase, set under Counting direction is specified by whether the counting direction is to be defined by the user program (internal direction con- trol) or by an input (external direction control). Define the initial counting direc- tion.
Under Reset to initial values you can define the initial count value and the initial ref- erence value and define whether resetting to these values is to be carried out by an external input and at which signal level. Resetting is active for as long as the set sig- nal level is present. You can change the initial count value and the reference value during runtime using the CTRL_HSC statement.
Under Event configuration you can set the event at which the counter is to generate a process interrupt, as well as the name of the interrupt event. The events are:
Generate interrupt for counter value equals reference value event, Generate interrupt for external reset event and Generate interrupt for direction change event. Provide the event with a name, and assign a process interrupt organization block to it.
The HW interrupt drop-down list contains all previously created organization blocks with the start event Hardware interrupt. You can create a new process inter- rupt OB using the Add object button.
Hardware inputs lists those inputs occupied by counters, together with the maxi- mum achievable counting frequency.
Under I/O addresses/HW identifier you can set the addresses of the peripheral inputs at which the counter is to output the actual count value. In the Process image drop-down list you can set whether the transfer is to be to the input process image (Cyclic PI). The hardware ID of the counter is also specified in this tab (HW ID); use this for assigning the configured counter to the CTRL_HSC statement on the HSC parameter.
CTRL_HSC statement
The CTRL_HSC statement controls a high-speed counter. CTRL_HSC can be found in the program elements catalog under Technology and Counters. To call the state- ment, drag CTRL_HSC with the mouse into the open block. Each CTRL_HSC call
requires an instance data record, which can be either in a separate block (single instance) or – if the call is made in a function block – in the instance data block of the calling function block (multi-instance).
The CTRL_HSC is executed if “1” is present at the enabling input or if “current” flows into the EN input or if EN is not connected. The enabling output ENO is then “1”.
If execution of the function is not enabled (EN = “0”) or if an error occurs during ex- ecution of the statement, ENO is set to signal state “0”.
The HSC ID can be found either in the System constants tab in the default tag table or the properties of the CPU in the High-speed counters (HSC) group under the activated and applied counter under General and Name. At the HSC parameter, enter this name or select it from the drop-down list. You can also specify the numerical value of the HSC ID, which is shown in the System constants tab or in the counter properties under Hardware ID, as a constant or variable.
With signal state “1”, the DIR parameter sets the counting direction which is speci- fied on the NEW_DIR parameter (+1 = up, –1 = down). Signal state “0” on the DIR pa-
Fig. 17.3 Call box for a high-speed counter HSC CTRL_HSC
PERIOD HSC
NEW_DIR DIR
NEW_CV CV
NEW_RV RV
NEW_PERIOD BUSY STATUS
Controlling a high-speed counter (HSC) Instance data
A high-speed counter (HSC) is a function integrated in the CPU module. A high-speed counter permits the counting of pulses and a frequency measurement up to 100 kHz or 200 kHz.
The CTRL_HSC statement controls a high-speed counter.
Calling of CTRL_HSC requires an instance data record which can be either in a separate data block (single instance) or in the instance data block of the calling function block (multi-instance).
Declaration Name
EN ENO HSC DIR CV RV
NEW_RV PERIOD
NEW_PERIOD NEW_DIR
BUSY NEW_CV
STATUS - - INPUT INPUT INPUT INPUT
INPUT INPUT
INPUT INPUT
OUTPUT INPUT
OUTPUT
BOOL BOOL HW_HSC BOOL BOOL BOOL
DINT BOOL
INT INT
BOOL DINT
WORD
Enabling input Enabling output
HSC ID (1 ... 6, is created when activating the HSC) Set a new counting direction (with signal state “1”) Set a new count value (with signal state “1”) Set a new reference value (with signal state “1”)
New reference value
Set a new time interval (with signal state “1”)
New time interval
New counting direction (+1 = up, –1 = down)
Job being processed (with signal state “1”) New count value
Job status Description Data type
rameter has no effect. The parameter is only effective if the counter is configured with internal specification of the counting direction.
With signal state “1”, the CV parameter sets the count value to the initial count val- ue which is specified on the NEW_CV parameter. Signal state “0” on the CV param- eter has no effect.
With signal state “1”, the RV parameter sets the reference value to the value which is specified on the NEW_RV parameter. Signal state “0” on the RV parameter has no ef- fect.
With signal state “1”, the PERIOD parameter sets the time interval for the measur- ing period to the value which is specified on the NEW_PERIOD parameter. Signal state “0” on the PERIOD parameter has no effect. The PERIOD parameter is only ef- fective if the counter is configured with the Frequency counting mode.
The BUSY parameter shows with signal state “1” that a triggered job is still being processed following completion of the CTRL_HSC statement (should not occur with the high-speed counters of a CPU 1200). The STATUS parameter shows the job sta- tus and specifies any error messages.