Acer aspire ES1 572 compal b5w1s LA d671p rev 1 0 схема

S0 ONON N/AN/APower Plane Descrip tion +VCC_G T Processor Graphics Power Rails STATE SIGNAL S3 Suspend to RAM S4 Suspend to Disk S5 Soft OFF ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF L

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2016.01.18 Rev: 1.0 LA-D671P

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Cover Sheet

Custom

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page 25

USB 3.0 conn x1

48MH z

HDA Codec ALC233

Touch Pad PS2 (from EC) / I2C (from SOC) Int.KBD

page 29

ENE KB9022

page 30 page 26

port 8

SATA CDROM Conn.

page 26

SATA HDD Conn

PCIe 1.0 2.5G T/s

on Sub/B

SPI

page 9

SPI ROM 64Mb

DDI2

LAN(GbE)

Card Reader RTS5170

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC

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BOM Structure Table

+1.8VALW_PRIM +1.8V Always power rail

+1.2V_V D D Q

ONON+VCC_COR E

Voltage Rails +19V_VIN +19VB

Adapter power supply

AC or battery power rail for power circuit

Processor IA Cores Power Rail

Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF

S0

ONON

N/AN/APower Plane Descrip tion

+VCC_G T Processor Graphics Power Rails

STATE SIGNAL

S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

ON ON ON

ON

OFF OFF OFF

OFF OFF OFF OFF OFF LOW LOW LOW

LOW LOW LOW HIGH

HIGH HIGH S0 (Full ON) HIGH HIGH HIGH ON ON ON ON

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power State

Board ID Table for AD channel

+VCC _S A System Agent power rail

BOM Option Table

CONN@

Connector

BOM Option Table

+1.0VS_VCCS T G +1.0VALW_PRIM Gated version of VCCST ON

+1.0V_VCC ST U Sustain voltage for processor in Standby modes ON

+5VS System +5V power rail

+5V Always power rail

O FF O FF

O FFN/A N/A

ON ON*1

ONON

O FFON

ON*1

O FF

Tit le

Security Classification Compal Secret Data

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D RVO N

+VCC_CORE

NCP81151MNTBG (PU9003) +VCC_GT

+VCC_SA

NCP81253MNTBG (PU9004)

+1.2VP

RT8207KGQW (PU501)

SYSO N

+0.6VSPSM_PG_CTR L

+3VLP

+5VALWP

SY8286CRAC (PU402)

5V_ EN

JUMP (PJ501) JUMP (PJ502)

+1.2V_VDDQ +0.6VS_VTT

JUMP (JPC1,JPC2) +1.2V_VDDQ_CPU

R-Short (RC208) +1.2V_VDDQC R-Short

(RC141) +1.2V_VCCSFR_OC

JUMP (PJ402) +5VALW

SY6288C20AAC (US21)

USB_EN

+USB3_VCCA

JUMP (JPQ2) +5VS

R-Short (RX8) +TS_PWR AP2330W

(UY1) +HDMI_5V_OUT R-Short

(RO3) +5VS_HDD

0 ohm (RO2) +5VS_ODD JUMP

(JPA1) +VDDA R-Short

(RF1) +VCC_FAN1

JUMP (PJ601) +1.0VALW_PRIM

+1.0VALWP

SY8288RAC (PU601)

EN_1VA LW

R-Short (RC173) +3VALW_DSW JUMP

(JPC7) +3VALW_PRIM

R-Short (RC197) +3VALW_1.8VALW_PGPPA R-Short

(RC161) +3VALW_PGPPB R-Short

(RC163) +3VALW_PGPPC R-Short

(RC172) +3VALW_1.8VALW_PGPPD R-Short

(RC167) +3VALW_PGPPE R-Short

(RC187) +3VALW_PGPPG R-Short

(RC171) +3VALW_RTC

SY6288C20AAC (UL1) +3V_LAN SY6288C20AAC

(UK1) +3V_PTP

TP_PWR_E NLAN_PWR _ EN

SY6288C20AAC (UM1) +3VS_WLAN

W LAN _O N

EM5209VF (UQ1)

SUSP#

EM5209VF (UQ1)

SUSP#

+5VS_OUT

R-Short (RC178) +1.8VS_3VS_PGPPA

SY6288C20AAC (UX1)

SOC_ENVD D

+LCDVDD

0 ohm (RM1) +3VS_WLAN R-Short

(RA2) +3VS_DVDDIO R-Short

(RA5) +3VS_DVDD

G971ADJF11U (PU702)

SPO K

+1.8VALWP JUMP (PJ702) +1.8VALW_PRIM EM5209VF (UC5) +1.8VS R-Short (RA6) +1.8VS_VDDA

R-Short (RC148) +1.0VALW_APLL JUMP

(JPC9) +1.0VALW_MPHYPLL

JUMP (PJ401) +3VALW

+3VALWP3V_ EN SY8286BRAC

(PU401)

R-Short (RC162) +1.0VALW_DTS R-Short

(RC169) +1.0VALW_CLK6_24TBT R-Short

(RC164) +1.0VALW_VCCCLK2 R-Short

(RC190) +1.0VALW_CLK4_F100OC R-Short

(RC152) +1.0VALW_CLK5_F24NS

+1.0VALW_MPHYAON

R-Short (RC175) EM5209VF (UC5) +1.0V_VCCSTU AOZ1336

(UC8) +1.0VS_VCCSTG_IO

R-Short (RC188) +1.0VS_VCCSTG

SYSO N

SUSP#

JUMP (JPC5) +VCCIO

R-Short (RC140) +1.0V_VCCST

R-Short (RC143) +1.0V_VCCSFR

R-Short (RC209) +1.0VALW_MPHYGT R-Short

(RC149) +1.0VALW_AMPHYPLL R-Short

(RC176) +1.0VALW_SRAM R-Short

(RC156) +1.0VALW_APLLEBB

LD O

APL5336KAI (PU502) +2.5VP

SYSO N

APL5336KAI (PU502) +2.5VP

SYSO N

TitleSize Document Number R e v

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

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79 80 SCL2 SDA2

7 6

77 78

CONN BATTERY EC_SMB_C K1

EC_SMB_CK1_CHGR

0 ohm

EC_SMB_DA1 SCL1

0x16

Address(7 bit)

I2C Address Table BUS

EC_SMB_CK1 +3VLP BQ24780 (Charger IC) BATTERY PACK 0x12

0x2C

TM-P2969-001 (TP)

0xA4

I2C_1 (+3VS) I2C_0 (+3VS) Reserved (Touch Panel)

SOC_SML1CLK +3VALW_PRIM

1.0

SMBUS_Routing_Table

Custom

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+1.8VALW _PG +1.8VALW _PRIM

VR_PWRGD

PLT_RST#

PCH_PWROK (SYS_PWROK) VR_ON

+VCCPRIM_CORE/+1.0VALW _PRIM

+1.0V_VCCST U

+1.0VS_VCCS T G

+VCC_SA EC_VCCST_PG

+VCC_CORE / +VCC_GT H_CPUPW RGD

+RTCVCC SOC_RTCRST#

tCPU09 Min : 1 ms

tCPU16 Min : 0 ns tCPU00 Min : 1 ms

tPLT05 Min : Platform dependent

Title

1.0

Power Sequence

Custom

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Rev_0.53

DDPB_CTRLDATA

DDPC_CTRLDATA

Display Port B/C Detected

NC =Port is not detected.

PU =Port is detected

Funct i onal Str ap Def ini t i o n s

#543016 PDG2.0 P.873 PROC_POPIRCOM P/PCH_OPIRCOMP

PD 50ohm

#543016 PDG2.0 P.844

#544669 CRB1.1 P.52 EDRAM_OPIO_RCOMP/EOPIO_RCOM P

PD 50ohm SPI touch INT follow CRB

#545659 PCH EDS1.51 P.131 SCI capability is available on all GPIOs, while NMI and SMI capability is available on only select GPIOs.

Below are the PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧ GPP_C [ 23 : 22 ]

‧ GPP_ D [ 4 : 0 ]

‧ GPP_E [ 8 : 0 ] , GPP_E [ 16 : 13 ]

‧

#543016 PDG2.0 P.225

COMPENSATION PU for eDP

Trace width=5 mils,Spacing=25mil,Max length=600mils

#543016 PDG2.0 P.857

PU 1K to VCCST

EC_SCI# SOC internal PU

Reserved CATERR# for sight i ngs i ss ue c heck

For Intel debug, place to CPU side.

#543016 PDG2.0 P.629

CPU side CMC side

H_PECI

TP_INT#

CPU_POPIRCOMPPCH_OPIRCOMPEDRAM_OPIO_RCOMPEOPIO_RCOMP

CPU_XDP_TCK0SOC_XDP_TMSSOC_XDP_TRST#

SOC_XDP_TDISOC_XDP_TDO

CPU_XDP_TCK0SOC_XDP_TMSSOC_XDP_TRST#

PCH_JTAG_TCK1SOC_XDP_TDISOC_XDP_TDO

H_PROCHOT#_RH_THERMTRIP#

SOC_XDP_TDOCPU_XDP_TCK0

1 OF 20UC1A

SKL-U_BGA1356

@

DDI1_AUXN G50DDI1_AUXP F50

EDP_RCOMP

E52

EDP_AUXN E45EDP_AUXP F45EDP_DISP_UTIL B52

EDP_TXN[0] C47EDP_TXN[1] D46EDP_TXN[2] A45EDP_TXN[3] A47

EDP_TXP[0] C46EDP_TXP[1] C45EDP_TXP[2] B45EDP_TXP[3] B47

GPP_E13/DDPB_HPD0 L9GPP_E14/DDPC_HPD1 L7GPP_E15/DDPD_HPD2 L6GPP_E16/DDPE_HPD3 N9GPP_E17/EDP_HPD L10

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#543016 PDG2.0 P.190 Trace width/Spacing >= 20mils Place componment near SODIMM

DDR_VTT_CNTL to DDR VTT supplied ramped

<35uS (tCPU18)

ES Sample

#543016 PDG2.0 P.139 W=12-15 Space= 20/25 L=500mil

2015MOW02, Can't install Cap on DRAMRST Change PN to SA00007UR00.

+0.6V_B_VREFCADDR_PG_CTRL

DDR_A_D57DDR_A_D59

DDR_A_D48

DDR_A_D56DDR_A_D54DDR_A_D51DDR_A_D53DDR_A_D49

DDR_A_D61DDR_A_D55DDR_A_D52

DDR_A_D60DDR_A_D62

DDR_A_D7

DDR_A_D13DDR_A_D8

DDR_A_D15DDR_A_D11

DDR_A_D23

DDR_A_D30

DDR_A_D24

DDR_A_D18

DDR_A_D22

DDR_A_D29

DDR_A_D20DDR_A_D16

DDR_A_D25

DDR_A_D47DDR_A_D39

DDR_A_D33DDR_A_D35

DDR_A_D42

DDR_A_D38DDR_A_D40

DDR_A_D34DDR_A_D36

DDR_A_D43DDR_A_D37

DDR_A_D45DDR_A_D41

DDR_A_ODT0DDR_A_MA5DDR_A_MA6

DDR_A_CLK0DDR_A_CLK#0DDR_A_CLK1DDR_A_CLK#1

DDR_A_MA8

DDR_A_CKE1

DDR_A_CS#1

DDR_A_MA7DDR_A_MA12DDR_A_ACT#

DDR_A_BG1DDR_A_MA13DDR_A_MA14DDR_A_BA0DDR_A_MA2DDR_A_BA1DDR_A_MA10DDR_A_MA1DDR_A_MA3DDR_A_DQS#0DDR_A_DQS0DDR_A_DQS#1DDR_A_DQS1DDR_A_DQS#2DDR_A_DQS2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS3DDR_A_DQS4DDR_A_DQS#5DDR_A_DQS5DDR_A_DQS#6DDR_A_DQS6DDR_A_DQS#7DDR_A_DQS7

DDR_B_D3

DDR_B_D8

DDR_B_D13DDR_B_D4

DDR_B_D14

DDR_B_D7DDR_B_D10

DDR_B_D2DDR_B_D0

DDR_B_D15

DDR_B_D6DDR_B_D9DDR_B_D12

DDR_B_D19

DDR_B_D29DDR_B_D20

DDR_B_D31

DDR_B_D17

DDR_B_D25DDR_B_D28DDR_B_D30DDR_B_D27DDR_B_D22DDR_B_D18

DDR_B_D24DDR_B_D16

DDR_B_D32DDR_B_D34

DDR_B_D47

DDR_B_D35DDR_B_D38DDR_B_D41DDR_B_D44

DDR_B_D37

DDR_B_D42

DDR_B_D36

DDR_B_D56

DDR_B_D60

DDR_B_D62DDR_B_D51

DDR_B_D61DDR_B_D58

DDR_B_MA5DDR_B_MA6DDR_B_MA7DDR_B_MA12DDR_B_ACT#

DDR_B_BG1DDR_B_MA13DDR_B_MA14DDR_B_BA0DDR_B_MA2DDR_B_BA1DDR_B_MA10DDR_B_MA1DDR_B_MA3DDR_B_DQS#0DDR_B_DQS0DDR_B_DQS#1DDR_B_DQS1DDR_B_DQS#2DDR_B_DQS2DDR_B_DQS#3DDR_B_DQS#4DDR_B_DQS3DDR_B_DQS4DDR_B_DQS#5DDR_B_DQS5DDR_B_DQS#6DDR_B_DQS6DDR_B_DQS#7DDR_B_DQS7

DDR_B_CLK1DDR_B_CLK#1DDR_B_CLK0DDR_B_CKE0

DDR_DRAMRST#

DDR_A_ALERT#

DDR_B_PAR+0.6V_A_VREFCA

DDR_B_MA5 <20>DDR_B_MA6 <20>DDR_B_MA7 <20>DDR_B_MA12 <20>DDR_B_ACT# <20>DDR_B_BG1 <20>

DDR_B_MA2 <20>DDR_B_MA10 <20>DDR_B_MA1 <20>DDR_B_MA3 <20>DDR_B_DQS#0 <20>DDR_B_MA4 <20>DDR_B_DQS0 <20>DDR_B_DQS#1 <20>DDR_B_DQS1 <20>DDR_B_DQS#2 <20>DDR_B_DQS2 <20>DDR_B_DQS#3 <20>DDR_B_DQS3 <20>DDR_B_DQS#4 <20>DDR_B_DQS4 <20>DDR_B_DQS#5 <20>DDR_B_DQS5 <20>DDR_B_DQS#6 <20>DDR_B_DQS6 <20>DDR_B_DQS#7 <20>DDR_B_DQS7 <20>DDR_B_MA13 <20>

DDR_B_CLK#0 <20>DDR_B_CLK0 <20>DDR_B_CLK#1 <20>DDR_B_CLK1 <20>DDR_B_CKE0 <20>

DDR_B_CS#0 <20>DDR_A_ODT0 <19>

+1.2V_VDDQ+3VS+0.6V_A_VREFCA

Title

SKL-U_BGA1356

@

DDR_VREF_CA AY67DDR0_VREF_DQ AY68DDR1_VREF_DQ BA67DDR_VTT_CNTL AW67DDR0_ALERT# AW50

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AU52DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT48

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AY55

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AU48

DDR0_CKE[0] BA56DDR0_CKE[1] BB56DDR0_CKE[2] AW56DDR0_CKE[3] AY56

DDR0_CKN[0] AU53DDR0_CKN[1] AU55DDR0_CKP[0] AT53DDR0_CKP[1] AT55

DDR0_CS#[0] AU45DDR0_CS#[1] AU43

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AY50DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] BB50DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AT50

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA54DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AW54

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU46DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AY54DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# BA55

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AY51

DDR0_MA[3] BA50DDR0_MA[4] BB52

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BA51DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BA52DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AW52DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AY52DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BB54

DDR0_ODT[0] AT45DDR0_ODT[1] AT43

DDR0_PAR AT52

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU50DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AT46

DDR0_DQSP[0] AM69DDR0_DQSP[1] AT70DDR0_DQSP[2]/DDR0_DQSP[4] AY64DDR0_DQSP[3]/DDR0_DQSP[5] BA60DDR0_DQSP[4]/DDR1_DQSP[0] AY38DDR0_DQSP[5]/DDR1_DQSP[1] BA34DDR0_DQSP[6]/DDR1_DQSP[4] AY30DDR0_DQSP[7]/DDR1_DQSP[5] BA26

SKL- U

DDR CH - B

3 OF 20UC1C

SKL-U_BGA1356

@

DDR_RCOMP[0] AR18DDR_RCOMP[1] AT18DDR_RCOMP[2] AU18DDR1_ALERT# AN43

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] BB44DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] BA44

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AP52

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY43

DDR1_CKE[0] AN56DDR1_CKE[1] AP55DDR1_CKE[2] AN55DDR1_CKE[3] AP53

DDR1_CKN[0] AN45DDR1_CKN[1] AN46DDR1_CKP[0] AP45DDR1_CKP[1] AP46

DDR1_CS#[0] BB42DDR1_CS#[1] AY42

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BA46DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AY46DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AW46

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN48DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN50

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] BA43DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] AN52DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN53

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AY47

DDR1_MA[3] BB46DDR1_MA[4] BA47

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AY48DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BA48DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP48DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] BB48DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AP50

DDR1_ODT[0] BA42DDR1_ODT[1] AW42

DDR1_DQSP[0]/DDR0_DQSP[2] AH65DDR1_DQSP[1]/DDR0_DQSP[3] AG70DDR1_DQSP[2]/DDR0_DQSP[6] AR65DDR1_DQSP[3]/DDR0_DQSP[7] AR60DDR1_DQSP[4]/DDR1_DQSP[2] AR38DDR1_DQSP[5]/DDR1_DQSP[3] AR32DDR1_DQSP[6] AR27DDR1_DQSP[7] AR21

@

RC10100K_0402_5%

Trang 9

( to EC, Thermal sensor)

To EC

SPI ROM ( 8MByte )

ESPI / LPC Bus ESPI : +1.8V LPC : +3.3V

RPC5 and RC52 are close UC2

SPI ROM

SPI Touch

Strap Pin

2015MOW06 no need PU1K on SPI_IO2/IO3

Change RC144~RC147, RC45 to 15ohm when use ESPI

*

SML0ALERT# / GPP_C5 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# ) eSPI or LPC

0 = LPC is selected for EC > For KB9022/9032 Use

1 = eSPI is selected for EC > For KB9032 Only.

*

SMBALERT# / GPP_C2 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# ) TLS Conf i dent ial i ty

0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no conf i dent ial i ty).

1 = Enable Intel ME Crypto (TLS) (with conf i dent ial i ty) Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

SOC_SPI_IO2

SOC_SPI_IO2_0_R

SOC_SPI_CLKSOC_SPI_SISOC_SPI_SO

EC_KBRST#_RTPM_SERIRQ

SOC_SML1ALERT#

SOC_SML0CLKSOC_SML0DATASOC_SML1CLKSOC_SML1DATA

SOC_SMBCLKSOC_SMBDATASOC_SMBALERT#

SOC_SML0ALERT#

CLKOUT_LPC0PM_CLKRUN#

LPC_FRAME#

LPC_AD2LPC_AD0LPC_AD3LPC_AD1

ESPI_RST#

SOC_SML0CLKSOC_SML0DATA

SOC_SMBCLK_1SOC_SMBDATA_1

SOC_SMBDATA_1SOC_SMBCLK

D S

QC2B2N7002KDW_SOT363-6

4

DI(IO0) 5DO(IO1)

2

/WP(IO2)

3

VCC 8/HOLD(IO3) 7/CS

GPP_A1/LAD0/ESPI_IO0 AY13GPP_A2/LAD1/ESPI_IO1 BA13GPP_A3/LAD2/ESPI_IO2 BB13GPP_A4/LAD3/ESPI_IO3 AY12GPP_A5/LFRAME#/ESPI_CS# BA12GPP_A14/SUS_STAT#/ESPI_RESET# BA11

GPP_A9/CLKOUT_LPC0/ESPI_CLK AW9GPP_A10/CLKOUT_LPC1 AY9GPP_A8/CLKRUN# AW11

CS#

1

SO/SIO1 2WP#

3

GND

4

VCC 8HOLD#

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to GPIO funct i onali t y ( as i nput) If S DI O i nt erf ac e i s not used, the signals can be used as GPIOs instead

If the GPIO funct i onali t y i s al s o not us ed, t he si gnal s can be lef t as no- c onnect.

*

SPKR / GPP_B14 (Internal Pull Down):

(Sampled:Rising edge of PCH_PWROK)

TOP Swap Override

0 = Disable TOP Swap mode.

1 = Enable TOP Swap Mode.

HDA for AUDIO

Intel HD Audio link capabilit i es

> Two SDI signals to support two external codecs.

> Drivers variable requency (5MHz to 24MHz) BCLK to support:

SDO double pumped up to 48 Mb/s

SDI's single pumped up to 24 Mb/s

> Provides cadence for 44.1 kHz based sample rate output.

> Support 1.5V, 1.8V, and 3.3V modes.

HDA_SDO / I2S_TXD0 (Internal Pull Down):

(Sampled: Rising edge of PCH_PWROK )

Flash Descriptor Security Override

0 = Enable security measures def i ned i n t he Fl as h

Descriptor

1 = Disable Flash Descriptor Security (override) This

strap should only be asserted high using external

pull-up in manufacturing/debug environments ONLY

#543016 PDG2.0 P.879

#543016 PDG2.0 P.551

#543016 PDG2.0 P.393

HDA_BIT_CLKHDA_SYNC

HDA_RST#

HDA_SDIN0HDA_SDOUT

SDIO/SDX C

7 OF 20UC1G

GPP_F23 AF13

RC13310K_0402_5%

GPP_F13/EMMC_DATA0 AP2GPP_F14/EMMC_DATA1 AP1GPP_F15/EMMC_DATA2 AP3GPP_F16/EMMC_DATA3 AN3GPP_F17/EMMC_DATA4 AN1GPP_F18/EMMC_DATA5 AN2GPP_F19/EMMC_DATA6 AM4GPP_F20/EMMC_DATA7 AM1GPP_F21/EMMC_RCLK AM2GPP_F22/EMMC_CLK AM3GPP_F12/EMMC_CMD AP4EMMC_RCOMP AT1

12

Trang 11

Rev_0.53

Place at RAM DOOR

#543016 PDG2.0 P.599

PROCPWRGD is used only for power sequence

debug and is not required to be connected to

anything on the plat f or m

WAKE# (DSX wake event)

10 KΩ pull- up t o Vcc DS W 3_3.

The pull-up is required even if PCIe* interface

is not used on the plat f or m

Change PN to SJ10000Q400

XCLK_BIASREF T:50ohm S:12/15 L:1000 Via:2

Follow 2014MOW48 Skylake U PU 2.7k ohm to 1V Cannonlake U PD 60.4 ohm

2014M OW4 8:

Skylake-U use 24M 50 ohm ESR Cannonlake U use 38.4M 30 ohm ESR

EC internal PU PCH internal PU

Note for VCCST_PWRGD

1 1.0V tolerance

2 PDG2.0 P.598 Figure43-5 note17: when failure events,

VCCST_PWRGD and PCH_PWROK de-assert at the same t i me

From EC(open-drain)

Default : GPI

SOC_XTAL24_INSOC_XTAL24_OUTSOC_SRTCRST#

H_CPUPWRGDSYS_PWROKPCH_PWROKPCH_DPWROKSUSPWRDNACKSUSACK#

CLKREQ_PCIE#2CLK_PCIE_N2

CLKREQ_PCIE#5

SUSCLKSOC_XTAL24_INSOC_XTAL24_OUT

SOC_RTCX2SOC_SRTCRST#

SOC_RTCRST#

CLKREQ_PCIE#1CLKREQ_PCIE#2

EC_RSMRST#

LAN_WAKE#

PBTN_OUT#_R

PCH_PWROKSYS_PWROK

CLKREQ_PCIE#0

SOC_RTCX1SOC_RTCX2CLKREQ_PCIE#3

H_CPUPWRGDSYS_RESET#

PCH_PWROKSYS_PWROK

EC_RSMRST#

CLKREQ_PCIE#0CLKREQ_PCIE#4

Title

10 OF 20UC1J

@ESD@

12

YC232.768KHZ_9PF_X1A000141000200

@

12

SKL- USYSTEM POWER MANAGEMENT

11 OF 20UC1K

GPP_A11/PME# AU11INTRUDER# AP16GPP_B11/EXT_PWR_GATE# AM10GPP_B2/VRALERT# AM11

RC118100K_0402_5%

RPC11

10K_0804_8P4R_5%

18273645

CC168.2P_0402_50V8D

1

2

CC156.8P_0402_50V8C

27

36

45

Trang 12

1 1

GSPI0_MOSI /GPP_B18 (Internal Pull Down):

(Rising edge of PCH_PWROK)

No Reboot

0 = Disable No Reboot mode > AAX05 Use

1 = Enable No Reboot Mode (PCH will disable the TCO Timer system reboot feature) This funct i on i s us ef ul when running ITP/XDP.

GSPI1_MOSI / GPP_B22 (Internal Pull Down):

(Rising edge of PCH_PWROK) Boot BIOS Strap Bit

0 = SPI Mode > AAX05 Use

B5W1S

Project_ID0 Project_ID1

Reserved Reserved

*

0 1

SkyLake KabyLake

CPU_ID

TS_ENGSPI0_MOSI

GSPI1_MOSI

UART_2_CTXD_DRXDUART_2_CCTS_DRTS

I2C_0_SCLI2C_0_SDAI2C_1_SDAI2C_1_SCLI2C_2_SDAI2C_2_SCLI2C_3_SDAI2C_3_SCLI2C_4_SDAI2C_4_SCL

ISH_I2C0_SDAISH_I2C0_SCL

I2C_5_SDAI2C_5_SCL

ISH_I2C1_SCLISH_I2C1_SDA

ISH_I2C0_SDAISH_I2C0_SCL

PROJECT_ID1

PROJECT_ID0

I2C_0_SDAI2C_0_SCLI2C_1_SDAI2C_1_SCL

+1.8VS+3VS

SKL-U_BGA1356

@

GPP_A12/BM_BUSY#/ISH_GP6 AP13

GPP_A18/ISH_GP0 AY8GPP_A19/ISH_GP1 BA8GPP_A20/ISH_GP2 BB7GPP_A21/ISH_GP3 BA7GPP_A22/ISH_GP4 AY7GPP_A23/ISH_GP5 AW7

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U1

GPP_D16/ISH_UART0_CTS#/SML0BALERT# U4GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U2

GPP_D15/ISH_UART0_RTS# U3

GPP_D5/ISH_I2C0_SDA M4GPP_D6/ISH_I2C0_SCL N3GPP_D7/ISH_I2C1_SDA N1GPP_D8/ISH_I2C1_SCL N2GPP_D9 P2

GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD11GPP_F11/I2C5_SCL/ISH_I2C2_SCL AD12

Trang 13

DEVSLP[2:0] Implementat i on DEVSLP is a host-controlled hardware signal which enables a SATA host and device to enter an ultra-low interface power state, including the possibility to completely power down host and device PHYs.

The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.

When hi gh, DE VSL P r equests t he SAT A devi c e t o ent er i nt o t he DE VSL P po wer st at e

‧ When l o w, DE VSL P r equests t he SAT A devi c e t o exi t fr o m t he DE VSL P po wer st at e

‧ and transit i on t o ac t i ve s tate

SATA General Purpose (SATAGP[2:0]) Signals The pr oc ess or pr ovi des t hr ee SAT A gener al pur pos e i nput si gnal s, SAT AGP[ 2: 0] f or S KL U

‧ These signals can be conf i gur ed as i nt erl oc k s wit c h i nputs c orr es pondi ng t o a gi ven SAT A port

When us ed as an i nt erl oc k s wit c h st at us i ndi c a t i on, thi s s i gnal s houl d be dr i ven to 0

‧

to indicate that the switch is closed and to a 1 to indicate that the switch is open

If mec hani c al pr es enc e s wit c hes will not be us ed on t he pl a t fo rm, SAT AGP[2:0]

‧ signals can be conf i gur ed as GPP_E[ 2: 0] GPI Os si gnal s.

NGFF WLAN+BT(Key E)

GLAN

When PCIE8/SATA1A is used

as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

2015MOW10, USB2_ID Connected to GND Directly

N A

Unused OC pin need set to GPI.

TO D/B CR

USB20_N2USB20_N3

PCIE_CRX_DTX_N6PCIE_CRX_DTX_P6PCIE_CTX_DRX_P6

USB2_IDUSB2_VBUSSENSE

Title

Trang 14

#543016 PDG2.0 P.750 +1.35V_VDDQ_CPU : 4x 10uF 0402 3x 22uF 0603

BSC SidePSC Side

#543016 PDG2.0 P.750 +VCCIO : 4x 1uF 0402

PSC Side

BSC Side

#543016 PDG2.0 P.750 +1.35V_VDDQC : 1x 10uF

#543016 PDG2.0 P.750 +1.0V_VCCSFR : 1x 1uF

#543016 PDG2.0 P.750 +1.35V_VCCSFR_OC : 1x 1uF

#543016 PDG2.0 P.750 +1.0V_VCCSTG : 1x 1uF (Placeholder)

Reference GND as possible.

VCCSA_SENSE

VCCIO_SENSEVSSIO_SENSEVSSSA_SENSE

EN_1.8VSEN_1.0V_VCCSTU

+1.2V_VDDQ_CPU

+1.2V_VDDQ

+1.0VS_VCCSTG

+1.0V_VCCST+1.0VS_VCCSTG+1.2V_VCCSFR_OC+1.0V_VCCSFR

+1.8VALW_VS

+1.0V_VCCSTU+1.0VALW_PRIM

+1.2V_VDDQC+1.2V_VDDQ_CPU

+1.8VALW_PRIM

+1.0VALW_PRIM_JP

+5VALW

Title

CC951000P_0402_50V7K

CC96.1U_0402_16V7K1

VOUT 7VOUT 8VIN

@12

UC6

TPS22961DNYR_WSON8

GND 5ON

4

VOUT 6VIN2

14 OF 20UC1N

VCCIO_SENSE AM23

VCCSA AK23VCCSA AK25VCCSA G23VCCSA G25VCCSA G27VCCSA G28VCCSA J22VCCSA J23VCCSA J27VCCSA K23VCCSA K25VCCSA K27VCCSA K28VCCSA K30

VSSIO_SENSE AM22VSSSA_SENSE H21VCCSA_SENSE H20

7

CT1 12VOUT1 14

VOUT2 8

VOUT1 13VIN1

2

CC127.1U_0402_16V7K1

2

Trang 15

+CHGRTC BAT54C(VF) +RTCVCC

3.383V(M A X)

240 mV 3.143V Result : Pass

SPI Touch

cap place close AK19.

W=1 0 m il

W=20mils RTC Battery

CC77,CC78 near AK17 (<3 mm)

CC86 near A10 (<3 mm) CC87 near K17 (<3 mm)

+1.0VALW_CLK6_24TBT+RTCVCC

+1.0VALW_APLL+1.0VALW_CLK4_F100OC

+1.0VALW_PRIM

+1.0VALW_MPHYAON

+1.0VALW_AMPHYPLL+1.0VALW_APLL

+1.0VALW_CLK5_F24NS

+1.0VALW_PRIM+3VALW_DSW

+3VALW_HDA+3VALW_SPI

+3VALW_PGPPC+3VALW_1.8VALW_PGPPD+3VALW_PGPPE+1.8VALW_PRIM+3VALW_PGPPG

+1.0VALW_SRAM

+3VALW_PRIM

+1.0VALW_PRIM+1.0VALW_APLLEBB

+3VALW_1.8VALW_PGPPA+3VALW_PGPPB

+1.0VALW_CLK6_24TBT+1.0VALW_PRIM

+1.0VALW_PRIM +3VALW_PRIM +1.8VALW_PRIM

+1.0VALW_MPHYPLL+1.0VALW_PRIM

+RTCBATT

+RTCVCC+CHGRTC

+1.0VALW_AMPHYPLL

+1.0VALW_SRAM

+1.0VALW_APLLEBB

Title

CC83

12

2

CC761U_0402_6.3V6K

@12

12

15 OF 20UC1O

SKL-U_BGA1356

@

GPP_B0/CORE_VID0 AN11GPP_B1/CORE_VID1 AN13

12

2

CC74

12

CC86

12

CC631U_0402_6.3V6K

CC721U_0402_6.3V6K

12

CC911U_0402_6.3V6K

@12

12

CC12322U_0603_6.3V6M

12

CC73

12

2

CC102

12

Trang 16

1 1

Trace Length < 25 mils

For CPU2+3e SKU

Trace Length < 25 mils

Place the PU resistors close to CPU

For CPU2+3e SKU

Rev_0.53

#544924 SKL EDS1.2 P.141VCCOPC 1.0V 3.2AVCC_OPC_1P8 1.8V 50mAVCCEOPIO 0.8V,1.0V 2A

+1.0VS(SUSP#)

#544924 SKL EDS1.2 P.134 VCC U(15W)-dual core GT2 29A(MAX) 0.55-1.52V

#544924 SKL EDS1.2 P.136 VCCGT U(15W)-dual core GT2 31A(MAX) 0.55-1.5V

To VR

#543016 PDG2.0 P.273

VCCGT_SENSEVSSGT_SENSE

VCCOPC_SENSE

VCCEOPIO_SENSEVSSEOPIO_SENSE

SOC_SVID_CLKSOC_SVID_DATSOC_SVID_ALERT#

SOC_SVID_ALERT#

VCCGTX_SENSEVSSGTX_SENSESOC_SVID_DAT

Title

SKL- UCPU POWER 1 OF 4

12 OF 20UC1L

VIDALERT# B63VIDSCK A63VIDSOUT D64VCCSTG_G20 G20

RSVD_K32

K32

VSS_SENSE E33RSVD_AK32

AK32

SKL- UCPU POWER 2 OF 4

13 OF 20UC1M

VCCGTX_AK42 AK42VCCGTX_AK43 AK43VCCGTX_AK45 AK45VCCGTX_AK46 AK46VCCGTX_AK48 AK48VCCGTX_AK50 AK50VCCGTX_AK52 AK52VCCGTX_AK53 AK53VCCGTX_AK55 AK55VCCGTX_AK56 AK56VCCGTX_AK58 AK58VCCGTX_AK60 AK60VCCGTX_AK70 AK70VCCGTX_AL43 AL43VCCGTX_AL46 AL46VCCGTX_AL50 AL50VCCGTX_AL53 AL53VCCGTX_AL56 AL56VCCGTX_AL60 AL60VCCGTX_AM48 AM48VCCGTX_AM50 AM50VCCGTX_AM52 AM52VCCGTX_AM53 AM53VCCGTX_AM56 AM56VCCGTX_AM58 AM58VCCGTX_AU58 AU58VCCGTX_AU63 AU63VCCGTX_BB57 BB57VCCGTX_BB66 BB66VCCGTX_SENSE AK62VSSGTX_SENSE AL61VSSGT_SENSE

J69

Trang 17

SKL-U_BGA1356

@

VSSAT63VSSAT68VSSAT71VSSAU10VSSAU15VSSAU20VSSAU32VSSAU38VSSAV1VSSAV68VSSAV69VSSAV70VSSAV71VSSAW10VSSAW12VSSAW14VSSAW16VSSAW18VSSAW21VSSAW23VSSAW26VSSAW28VSSAW30VSSAW32VSSAW34VSSAW36VSSAW38VSSAW41VSSAW43VSSAW45VSSAW47VSSAW49VSSAW51VSSAW53VSSAW55VSSAW57VSSAW6VSSAW60VSSAW62VSSAW64VSSAW66VSSAW8VSSAY66VSSB10VSSB14VSSB18VSSB22VSSB30VSSB34VSSB39VSSB44VSSB48VSSB53VSSB58VSSB62VSSB66VSSB71VSSBA1VSSBA10VSSBA14VSSBA18VSSBA2VSSBA23VSSBA28VSSBA32VSSBA36

VSSBA45

SKL - U

GND 1 OF 3

16 OF 20UC1P

SKL-U_BGA1356

@

VSSA5VSSA67VSSA70VSSAA2VSSAA4VSSAA65VSSAA68VSSAB15VSSAB16VSSAB18VSSAB21VSSAB8VSSAD13VSSAD16VSSAD19VSSAD20VSSAD21VSSAD62VSSAD8VSSAE64VSSAE65VSSAE66VSSAE67VSSAE68VSSAE69VSSAF1VSSAF10VSSAF15VSSAF17VSSAF2VSSAF4VSSAF63VSSAG16VSSAG17VSSAG18VSSAG19VSSAG20VSSAG21VSSAG71VSSAH13VSSAH6VSSAH63VSSAH64VSSAH67VSSAJ15VSSAJ18VSSAJ20VSSAJ4VSSAK11VSSAK16VSSAK18VSSAK21VSSAK22VSSAK27VSSAK63VSSAK68VSSAK69VSSAK8VSSAL2VSSAL28VSSAL32VSSAL35VSSAL38VSSAL4VSSAL45VSSAL48VSSAL52VSSAL55VSSAL58VSSAL64

SKL-U_BGA1356

@

VSSF8VSSG10VSSG22VSSG43VSSG45VSSG48VSSG5VSSG52VSSG55VSSG58VSSG6VSSG60VSSG63VSSG66VSSH15VSSH18VSSH71VSSJ11VSSJ13VSSJ25VSSJ28VSSJ32VSSJ35VSSJ38VSSJ42VSSJ8VSSK16VSSK18VSSK22VSSK61VSSK63VSSK64VSSK65VSSK66VSSK67VSSK68VSSK70VSSK71VSSL11VSSL16VSSL17

Trang 18

Display Port Presence Strap

0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

1 : Disabled; No Physical Display Port

at t ac hed t o E mbedded Dis pl ay Port

For 2+3e Solut i on PM_ZVM#

Zero Voltage Mode: Control Signal to OPC

VR, when low OPC VR output is 0V.

PM_MSM#

Minimum Speed Mode: Control signal to VccEOPIO VR (connected only in 2 VR solut i on f or OPC).

Rev_0.53

#544669 CRB1.1 P.54

#544924 SKL EDS1.2 P.125 PROC_SELECT#

This pin is for compat i bili t y wit h f ut ur e plat f or ms It s houl d be unc onnect ed f or the processor.

CC79 near U11,U12 (<10 mm) 14MOW52, Connect U11, U12 to 1.8V for Cannonlake-U PCH compat i bili t y

CFG16CFG18

CFG0CFG2CFG4CFG6CFG8CFG10CFG12CFG14

@

T171

@T169

@

RC570_0402_5%

@

SKL- URESERVED SIGNALS-1

19 OF 20UC1S

SKL-U_BGA1356

@

RSVD_BA4 BA4RSVD_BB4 BB4

RSVD_A69 A69RSVD_B69 B69

RSVD_TP_BB68 BB68RSVD_TP_BB69 BB69

RSVD_TP_AK13 AK13RSVD_TP_AK12 AK12

TP4 BB5

TP5 AU5TP6 AT5

RSVD_B3 B3RSVD_A3 A3

ZVM# AR56

T173

@T176

@1

Trang 19

Check voltage tolerance of

VREF_DQ at the DIMM socketLayout Note:

Place near JDIMM1

DDR_A_CS#1DDR_A_CKE1

DDR_A_BA1

DDR_A_CLK#1DDR_A_CLK1

DDR_A_CS#0

SOC_SMBDATA_1SOC_SMBCLK_1

DDR_A_D4DDR_A_D0

DDR_A_D7DDR_A_D6

DDR_A_DQS#0DDR_A_DQS0

DDR_A_D1DDR_A_D5

DDR_A_D3DDR_A_D2

DDR_A_DQS1DDR_A_DQS#1

DDR_A_D21DDR_A_D20

DDR_A_D17

DDR_A_D28DDR_A_D29

DDR_A_D26DDR_A_D30

DDR_A_D24DDR_A_D25

DDR_A_D27DDR_A_D31DDR_A_DQS3DDR_A_DQS#3

DDR_A_D33DDR_A_D36

DDR_A_D35DDR_A_D34

DDR_A_D32DDR_A_D37

DDR_A_D38DDR_A_D39DDR_A_DQS4

DDR_A_DQS#4

DDR_A_D40DDR_A_D41

DDR_A_D42DDR_A_D43

DDR_A_D44DDR_A_D45

DDR_A_D46DDR_A_D47DDR_A_DQS5DDR_A_DQS#5

DDR_A_D51DDR_A_DQS6DDR_A_DQS#6

DDR_A_CKE0 DDR_A_CKE1DDR_A_BG1

DDR_A_MA9DDR_A_MA12

DDR_A_MA8

DDR_A_MA1

DDR_A_MA7DDR_A_MA11

DDR_A_MA4DDR_A_MA2

DDR_A_CLK#0DDR_A_PAR

DDR_A_MA14

DDR_A_MA10DDR_A_BA0DDR_A_BA1

DDR_A_CS#0

DDR_A_CS#1DDR_A_ODT1

DDR_A_MA16DDR_A_MA15

SOC_SMBCLK_1 SOC_SMBDATA_1DDR_A_SA0

DDR_A_SA2

DDR_A_SA0DDR_A_SA1

DDR_A_BG1DDR_A_ACT#

DDR_A_ALERT#

DDR_A_PAR

DDR_A_EVENT#

DDR_A_D13DDR_A_D12

DDR_A_D9

DDR_A_D8

DDR_A_D14

DDR_A_D19

DDR_A_D16DDR_A_D22

DDR_A_D57DDR_A_D56

DDR_A_D58DDR_A_D59

DDR_A_D60DDR_A_D63

DDR_A_D62DDR_A_D61

+1.2V_VDDQ

DDR4_DIMMA

Size Document Number R e v

DDR4_DIMMA

RD59240_0402_1%

CD1.1U_0402_16V7K

VSS 2DQ5

VSS5

VSS 6DQ1

VSS9

VSS 10DQS0_C

11 DM0*/DBI0* 12DQS0_T13

VSS 14VSS

DQ717

VSS 18VSS

DQ321

VSS 22VSS

23

DQ12 24DQ13

25

VSS 26VSS

27

DQ8 28DQ9

VSS31DQS1_C 32DM1*/DBI1*

33DQS1_T 34VSS

35

VSS 36DQ15

37

DQ14 38VSS

39

VSS 40DQ10

41

DQ11 42VSS

43

VSS 44DQ21

45

DQ20 46VSS

DQ1749

DQ16 50VSS

DQS2_C53DM2*/DBI2* 54DQS2_T

VSS57

DQ22 58DQ23

59

VSS 60VSS

DQ1963

VSS 64VSS

DQ2967

VSS 68VSS

DQ2571

VSS 72

DQ26

VSS85

VSS 86CB5_NC

VSS89

77

VSS 78DQ30

79

DQ31 80VSS

VSS 94DQS8_C

95 DM8*/DBI8* 96DQS8_T97

VSS 98VSS

99CB6_NC 100CB2_NC

VSS103

CB7_NC 104CB3_NC

VSS107

RESET* 108CKE0

109 CKE1 110VDD1

111

VDD2 112BG1

113 ACT* 114BG0

115

ALERT* 116VDD3

117 VDD4 118A12

119

A11 120A9

121

A7 122VDD5

123 VDD6 124A8

125

A5 126A6

VDD7129

VDD8 130A3

131

A2 132A1

133

EVENT* 134VDD9

135

VDD10 136CK0_T

137

CK1_T 138CK0_C

139

CK1_C 140VDD11

PARITY143

A0 144

BA1145

A10_AP 146VDD13

147

VDD14 148S0*

149

BA0 150A14_WE*

151A16_RAS* 152VDD15

ODT0155A15_CAS* 156S1*

VDD17159

VDD18 160ODT1

VDD19163VREFCA 164S3*/C1

165

SA2 166VSS

167

VSS 168DQ37

169

DQ36 170VSS

171

VSS 172DQ33

173

DQ32 174VSS

VSS181

DQ39 182DQ38

VSS185

DQ35 186DQ34

187

VSS 188VSS

189

DQ45 190DQ44

191

VSS 192VSS

193 DQ41 194DQ40

195

VSS 196VSS

DM5*/DBI5*

199

DQS5_T 200VSS

DQ46203

DQ47 204VSS

205

VSS 206DQ42

207VSS209DQ52211VSS213DQ49215VSS217DQS6_C219DQS6_T221VSS223DQ55225VSS227DQ51229VSS231DQ61233VSS235DQ56237VSS239DM7*/DBI7*

241VSS243DQ62245VSS247DQ58249

DQ43 208VSS 210DQ53 212VSS 214DQ48 216VSS 218DM6*/DBI6* 220VSS 222DQ54 224VSS 226DQ50 228VSS 230DQ60 232VSS 234DQ57 236VSS 238DQS7_C 240DQS7_T 242VSS 244DQ63 246VSS 248DQ59 250VSS

251SCL253VDDSPD255VPP1257VPP2259

VSS 252SDA 254SA0 256VTT 258SA1 260

GND 261GND 262

RD102_0402_1%

@1

2

Trang 20

DDR_B_CLK0DDR_B_CLK#0

DDR_B_CS#1DDR_B_CKE1

DDR_B_CLK1DDR_B_CLK#1DDR_B_BA1

DDR_B_ODT0DDR_B_CS#0

DDR_B_ODT1SOC_SMBCLK_1SOC_SMBDATA_1

DDR_B_MA16DDR_B_MA15

SOC_SMBCLK_1 SOC_SMBDATA_1

DDR_B_CKE0 DDR_B_CKE1DDR_B_BG1

DDR_B_MA9DDR_B_MA12

DDR_B_MA8

DDR_B_MA1

DDR_B_MA7DDR_B_MA11

DDR_B_MA4DDR_B_MA2

DDR_B_MA0

DDR_DRAMRST#

DDR_B_ACT#

DDR_B_SA2DDR_B_ALERT#

DDR_B_SA0DDR_B_SA1

DDR_B_CLK1DDR_B_CLK#1DDR_B_CLK0

DDR_B_CLK#0DDR_B_PAR

DDR_B_MA14

DDR_B_MA10DDR_B_BA0DDR_B_BA1

DDR_B_CS#0

DDR_B_CS#1DDR_B_ODT1

DDR_B_BG1DDR_B_ACT#

DDR_B_D15DDR_B_D14

DDR_B_D8DDR_B_D12

DDR_B_D11DDR_B_D10

DDR_B_D13DDR_B_D9

DDR_B_DQS#1DDR_B_DQS1

DDR_B_D4DDR_B_D0

DDR_B_D6DDR_B_D7

DDR_B_D5DDR_B_D1

DDR_B_D3DDR_B_D2

DDR_B_D20DDR_B_D21

DDR_B_D22DDR_B_D23

DDR_B_D16DDR_B_D17

DDR_B_D18DDR_B_D19

DDR_B_D29DDR_B_D28

DDR_B_D30DDR_B_D31

DDR_B_D24DDR_B_D25

DDR_B_D26DDR_B_D27DDR_B_DQS3DDR_B_DQS#3

DDR_B_D33DDR_B_D32

DDR_B_D35DDR_B_D34

DDR_B_D36DDR_B_D37

DDR_B_D38DDR_B_D39

DDR_B_D40DDR_B_D41

DDR_B_D43DDR_B_D46

DDR_B_D44DDR_B_D45

DDR_B_D47DDR_B_D42

DDR_B_D48DDR_B_D49

DDR_B_D50DDR_B_D51

DDR_B_D52DDR_B_D53

DDR_B_D55DDR_B_D54

DDR_B_D56DDR_B_D61

DDR_B_D59DDR_B_D58

DDR_B_D60DDR_B_D57

DDR_B_D62DDR_B_D63

DDR_B_SA0DDR_B_SA2

DDR_B_ALERT#

DDR_B_PAR

DDR_B_DQS8DDR_B_DQS#8

DDR4_DIMMB

1

2

CD30.1U_0402_16V7K

VSS 2DQ5

VSS5

VSS 6DQ1

VSS9

VSS 10DQS0_C

11 DM0*/DBI0* 12DQS0_T13

VSS 14VSS

DQ717

VSS 18VSS

DQ321

VSS 22VSS

23

DQ12 24DQ13

25

VSS 26VSS

27

DQ8 28DQ9

VSS31DQS1_C 32DM1*/DBI1*

33DQS1_T 34VSS

35

VSS 36DQ15

37

DQ14 38VSS

39

VSS 40DQ10

41

DQ11 42VSS

43

VSS 44DQ21

45

DQ20 46VSS

DQ1749

DQ16 50VSS

VSS57

DQ22 58DQ23

59

VSS 60VSS

DQ1963

VSS 64VSS

DQ2967

VSS 68VSS

DQ2571

VSS 72

DQ26

VSS85

VSS 86CB5_NC

VSS89

77

VSS 78DQ30

79

DQ31 80VSS

VSS 94DQS8_C

95 DM8*/DBI8* 96DQS8_T97

VSS 98VSS

99CB6_NC 100CB2_NC

VSS103

CB7_NC 104CB3_NC

VSS107

RESET* 108CKE0

109 CKE1 110VDD1

111

VDD2 112BG1

113 ACT* 114BG0

115

ALERT* 116VDD3

117 VDD4 118A12

119

A11 120A9

121

A7 122VDD5

123 VDD6 124A8

125

A5 126A6

VDD7129

VDD8 130A3

131

A2 132A1

133

EVENT* 134VDD9

135

VDD10 136CK0_T

137

CK1_T 138CK0_C

139

CK1_C 140VDD11

PARITY143

A0 144

BA1145

A10_AP 146VDD13

147

VDD14 148S0*

149

BA0 150A14_WE*

151A16_RAS* 152VDD15

ODT0155A15_CAS* 156S1*

VDD17159

VDD18 160ODT1

VDD19163VREFCA 164S3*/C1

165

SA2 166VSS

167

VSS 168DQ37

169

DQ36 170VSS

171

VSS 172DQ33

173

DQ32 174VSS

VSS181

DQ39 182DQ38

VSS185

DQ35 186DQ34

187

VSS 188VSS

189

DQ45 190DQ44

191

VSS 192VSS

193 DQ41 194DQ40

195

VSS 196VSS

DM5*/DBI5*

199

DQS5_T 200VSS

DQ46203

DQ47 204VSS

205

VSS 206DQ42

207VSS209DQ52211VSS213DQ49215VSS217DQS6_C219DQS6_T221VSS223DQ55225VSS227DQ51229VSS231DQ61233VSS235DQ56237VSS239DM7*/DBI7*

241VSS243DQ62245VSS247DQ58249

DQ43 208VSS 210DQ53 212VSS 214DQ48 216VSS 218DM6*/DBI6* 220VSS 222DQ54 224VSS 226DQ50 228VSS 230DQ60 232VSS 234DQ57 236VSS 238DQS7_C 240DQS7_T 242VSS 244DQ63 246VSS 248DQ59 250VSS

251SCL253VDDSPD255VPP1257VPP2259

VSS 252SDA 254SA0 256VTT 258SA1 260

GND 261GND 262

RD471K_0402_1%

Trang 21

USB20_N7_CAMERA

EDP_AUXN_CEDP_AUXP_CEDP_TXP0_C

EDP_TXP1_C

TS_ENUSB20_P6USB20_N6I2C_0_SCL

I2C_TS_INT#

I2C_TS_RST#

EDP_TXP0_CEDP_TXP1_C

EDP_AUXP_CEDP_AUXN_C

EDP_AUXN_CEDP_AUXP_C

+3VS

Title

@

CX34.7U_0603_6.3V6K

1

2

CX4.1U_0402_16V7K

RX6100K_0402_5%

12

LX1HCB2012KF-221T30_0805EMI@

SP01000XE00

1122334455667788991010111112121313141415151616171718181919202021212222232324242525262627272828292930303131323233333434353536363737383839394040

Tiêu đề	Acer Aspire ES1 572 Compal B5W1S LA D671P Rev 1 0 Schematic
Trường học	Compal Electronics, Inc.
Thể loại	Schematic Document
Năm xuất bản	2016
Thành phố	Taipei

Định dạng
Số trang	43
Dung lượng	2,22 MB