System-on-a-Chip: Design and Test For a listing of related titles from Artech House, turn to the back of this book System-on-a-Chip: Design and Test Rochit Rajsuman Artech House Boston • London www.artechhouse.com Library of Congress Cataloging-in-Publication Data Rajsuman, Rochit System-on-a-chip : design and test / Rochit Rajsuman p cm — (Artech House signal processing library) Includes bibliographical references and index ISBN 1-58053-107-5 (alk paper) Embedded computer systems—Design and construction Embedded computer systems—Testing Application specific integrated circuits—Design and construction I Title II Series TK7895.E42 R37 2000 621.39’5—dc21 00-030613 CIP British Library Cataloguing in Publication Data Rajsuman, Rochit System-on-a-chip : design and test — (Artech House signal processing library) Application specific integrated circuits — Design and construction I Title 621.3’95 ISBN 1-58053-471-6 Cover design by Gary Ragaglia © 2000 Advantest America R&D Center, Inc 3201 Scott Boulevard Santa Clara, CA 95054 All rights reserved Printed and bound in the United States of America No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized Artech House cannot attest to the accuracy of this information Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark International Standard Book Number: 1-58053-107-5 Library of Congress Catalog Card Number: 00-030613 10 Contents Preface xi Acknowledgment xiii Part I: Design 1 Introduction 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.4.1 1.4.2 1.4.3 Architecture of the Present-Day SoC Design Issues of SoC Hardware–Software Codesign Codesign Flow Codesign Tools Core Libraries, EDA Tools, and Web Pointers Core Libraries EDA Tools and Vendors Web Pointers References 14 15 18 21 21 23 28 29 Design Methodology for Logic Cores 33 2.1 2.2 SoC Design Flow General Guidelines for Design Reuse 34 36 v vi System-on-a-Chip: Design and Test 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.5 2.5.1 2.5.2 2.5.3 2.6 2.6.1 2.6.2 2.6.3 Synchronous Design Memory and Mixed-Signal Design On-Chip Buses Clock Distribution Clear/Set/Reset Signals Physical Design Deliverable Models Design Process for Soft and Firm Cores Design Flow Development Process for Soft/Firm Cores RTL Guidelines Soft/Firm Cores Productization Design Process for Hard Cores Unique Design Issues in Hard Cores Development Process for Hard Cores Sign-Off Checklist and Deliverables Sign-Off Checklist Soft Core Deliverables Hard Core Deliverables System Integration Designing With Hard Cores Designing With Soft Cores System Verification References 36 36 38 39 40 40 42 43 43 45 46 47 47 47 49 51 51 52 53 53 53 54 54 55 Design Methodology for Memory and Analog Cores 57 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.2 3.3.3 Why Large Embedded Memories Design Methodology for Embedded Memories Circuit Techniques Memory Compiler Simulation Models Specifications of Analog Circuits Analog-to-Digital Converter Digital-to-Analog Converter Phase-Locked Loops 57 59 61 66 70 72 72 75 78 Contents vii 3.4 3.4.1 3.4.2 3.4.3 High-Speed Circuits Rambus ASIC Cell IEEE 1394 Serial Bus (Firewire) PHY Layer High-Speed I/O References 79 79 80 81 81 Design Validation 85 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.3.3 Core-Level Validation Core Validation Plan Testbenches Core-Level Timing Verification Core Interface Verification Protocol Verification Gate-Level Simulation SoC Design Validation Cosimulation Emulation Hardware Prototypes Reference 86 86 88 90 93 94 95 95 97 101 101 103 Core and SoC Design Examples 105 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.4.1 5.4.2 Microprocessor Cores V830R/AV Superscaler RISC Core Design of PowerPC 603e G2 Core Comments on Memory Core Generators Core Integration and On-Chip Bus Examples of SoC Media Processors Testability of Set-Top Box SoC References 105 109 110 112 113 115 116 121 122 Part II: Test 123 Testing of Digital Logic Cores 125 6.1 SoC Test Issues 126 viii System-on-a-Chip: Design and Test 6.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 Access, Control, and Isolation IEEE P1500 Effort Cores Without Boundary Scan Core Test Language Cores With Boundary Scan Core Test and IP Protection Test Methodology for Design Reuse Guidelines for Core Testability High-Level Test Synthesis Testing of Microprocessor Cores Built-in Self-Test Method Example: Testability Features of ARM Processor Core Debug Support for Microprocessor Cores References 128 129 132 135 135 138 142 142 143 144 144 147 150 152 Testing of Embedded Memories 155 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 7.3.1 Memory Fault Models and Test Algorithms Fault Models Test Algorithms Effectiveness of Test Algorithms Modification With Multiple Data Background Modification for Multiport Memories Algorithm for Double-Buffered Memories Test Methods for Embedded Memories Testing Through ASIC Functional Test Test Application by Direct Access Test Application by Scan or Collar Register Memory Built-in Self-Test Testing by On-Chip Microprocessor Summary of Test Methods for Embedded Memories Memory Redundancy and Repair Hard Repair 156 156 157 160 161 161 161 162 163 164 164 164 169 171 171 171 7.3.2 7.4 Soft Repair Error Detection and Correction Codes 175 175 Contents ix 7.5 Production Testing of SoC With Large Embedded Memory References 176 177 Testing of Analog and Mixed-Signal Cores 181 8.1 8.1.1 8.1.2 8.1.3 8.2 Analog Parameters and Characterization Digital-to-Analog Converter Analog-to-Digital Converter Phase-Locked Loop Design-for-Test and Built-in Self-Test Methods for Analog Cores Fluence Technology’s Analog BIST LogicVision’s Analog BIST Testing by On-Chip Microprocessor IEEE P1149.4 Testing of Specific Analog Circuits Rambus ASIC Cell Testing of 1394 Serial Bus/Firewire References 182 182 184 188 191 192 192 195 197 200 200 201 204 Iddq Testing 207 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.3 9.4 9.5 Physical Defects Bridging (Shorts) Gate-Oxide Defects Open (Breaks) Effectiveness of Iddq Testing Iddq Testing Difficulties in SoC Design-for-Iddq-Testing Design Rules for Iddq Testing Iddq Test Vector Generation References 207 208 212 213 215 218 224 228 230 234 10 Production Testing 239 10.1 Production Test Flow 239 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.3.1 8.3.2 Appendix 263 11 When complex condition expressions are used that could be interpreted differently due to precedence rules 12 When blocking or nonblocking assignments have delays associated with them, since synthesis does not derive delays from the RTL statements 13 When RTL constructs are mixed inside gate-level designs Having few gates inside RTL is not a warning Also, continuous assign statements are allowed inside gate-level blocks 14 When a variable is set but not used inside the RTL code 15 Some compiler constructs such as “ifdef” or ”ifndef” may not be supported by synthesis tools—hence, Verilint gives warning 16 When input or an inout is declared as a registered variable 17 When the “or” operator is used in a potentially illegal way such as “a & b or c.” Some conditions and situations for which Verilint will issue errors are as follows: When an array is accessed by a negative index When an instance name (such as of a UDP) is in a sensitivity list An operand to a logical NOT operation has more than one bit since a logic gate cannot be inferred correctly by the tool When integer and constant case expressions are out of range Some synthesis tools not allow bit selection in the sensitivity lists and, hence, Verilint gives an error message Also, arrays cannot be used in the sensitivity lists When both leading and trailing edges are used in an “always” block When global variables are used inside functions or tasks All syntax errors and semantic errors in Verilog are also flagged as errors by Verilint This Page Intentionally Left Blank About the Author After receiving his Ph.D in electrical engineering from Colorado State University, Rochit Rajsuman served on faculty in the department of Computer Engineering and Science at Case Western Reserve University for almost seven years He later left academia to join LSI Logic as a product manager for test methodologies, where he productized a number of test solutions, including Iddq testing From LSI Logic, Dr Rajsuman moved to a media processor start-up He now works as Manager of Test Research at Advantest America R&D Center He has authored a number of patents and has published over 60 papers in refereed journals and conferences He has authored two books—Digital Hardware Testing (1992) and Iddq Testing for CMOS VLSI (1995), both published by Artech House He also co-edited the first book on Iddq testing, Bridging Faults and Iddq Testing (IEEE Computer Society Press, 1992) In 1995, Dr Rajsuman co-founded the IEEE Int Workshop on Iddq He also co-founded two other international conferences—the IEEE Int Workshop on Memory Technology, Design, and Testing, and the IEEE Int Workshop on Testing Embedded Core-based Systems He now serves on the Steering Committee of all three workshops Dr Rajsuman was also a founding member of the IEEE P1500 Working Group to define embedded core test standards He serves on the technical program committees of numerous other conferences, including the International Test Conference He is a senior member of IEEE, a Golden Core member of the IEEE Computer Society, and a member of both Tau Beta Pi and Eta Kappa Nu 265 This Page Intentionally Left Blank Index Rambus ASIC cell (RAC), 200–201 specifications, 72–79 testing, 181–204 testing by on-chip microprocessor, 195–97 testing specific, 200–204 See also cores Analog TAP (ATAP), 198 Analog-to-digital converters (ADCs), 72–75 accuracy, 74 AC parameters, 74–75 analog servo loop test, 188 aperture errors, 74, 187–88 conversion rate, 74 conversion time, 74 DC parameters, 73–74 design, 184–85 differential linearity error (DNL), 74, 186–87 dynamic differential linearity, 75 dynamic integral linearity, 75 effective number of bits (ENOB), 75, 187 full-scale range (FSR), 72 full-scale voltage error, 186 functional parameters, 72–73 gain error, 73, 186 Active ports, 161 AdcBIST, 192–94 Addressing faults, 156 Advanced high-performance bus (AHB), Advanced microcontroller bus architecture (AMBA), Algorithmic pattern generation (ALPG), 246 AMD 486DX core, 106, 108 Amplifiers See Sense amplifiers Analog BIST, 191–200, 254 adcBIST, 192–94 BISTMaxx, 192 categories, 191 environment, 191–92 fault-based methods, 191 functional methods, 191 pllBIST, 194–95 See also Analog cores; Built-in-self-test Analog boundary module (ABM), 198 Analog cores, 72–78, 182–204 analog-to-digital converter, 72–75, 184–88 BIST method for, 191–200 DFT method for, 191–200 digital-to-analog converter, 75–78, 182–84 phase-locked loops, 78–79, 188–91 267 268 System-On-a-Chip: Design and Test Analog-to-digital converters (ADCs) (continued) gain error shift, 73 input bandwidth, 74 input leakage currents, 74 integral linearity error (INL), 74, 186–87 LSB size, 73, 186 major transitions, 72 monotonicity, 74 offset error, 72, 185–86 output/encode rise/fall times, 75 output high impedance currents, 74 output logic levels, 73 output short-circuit current, 74 overvoltage recovery time, 75 power supply sensitivity ratio (PSSR), 74 reference voltage, 72 resolution, 72 signal-to-noise and distortion (SINAD), 75, 187 signal-to-noise ratio (SNR), 75, 187 spurious free dynamic range (SFDR), 75 supply currents, 73 testing, 184–88 testing by on-chip microprocessor, 195–97 total harmonic distortion (THD), 75, 187 transient response time, 75 two-tone intermodulation distortion, 75 uses, 184 See also Digital-to-analog converters (DACs) ARM processor advance microcontroller bus architecture (AMBA), 115 core, 106, 107 core characteristics, 147–49 core testability, 147–50 debug module, 151 in-circuit emulator (ICE), 150–51 test approaches, 149 testing illustration, 150 ASIC emulation tools, 27 vendor design, At-speed testing, 241–46 defined, 241 fly-by, 243–45 RTD and dead cycles, 241–43 speed binning, 245–46 See also Production testing BISTMaxx, 192 Bit-pattern faults, 156–57 Blue Logic Methodology, 12 Braunschweig Synthesis System (BSS), 21 Bridging defects, 208–13 behavior, 208, 212 detection, 212–13 examples, 209 potential divider model, 212 resistance, 212 simulation/modeling of, 208 See also Physical defects Bridging faults, 156 Built-in-self-repair (BISR), 37, 253 reason for, 171 schemes, 37 Built-in-self-test (BIST), 144–47 adcBIST, 192–94 analog, 191–200, 254 BISTMaxx, 192 defined, 144 implementation, 145 implementation illustration, 148 memory, 164–69, 253 pllBIST, 194–95 registers, 145–46 testing operation sequence, 146 Burn-in, 241 Bus functional model (BFM), 96 Cell coupling faults, 157 Cell stuck-at faults, 156 Checker pattern, 158 Circuit techniques, 61–66 floor planning and placement guidelines, 66 sense amplifiers, 61–66 Index Clock distribution, 39–40 rules, 39 schemes, 40 Clocks edge-synchronizing, 39 RTO, 233 RZ, 233 skew, minimizing, 39 trees, 39–40 Codesign, 14–21 defined, 14 flow, 15–18 interfaces, 18 methodology, 16 models, 14 partitions, 17 summary, 18 synthesis flow, 18 tools, 18–21, 23 See also Design Control scan path (CSP), 134 Core interface verification, 93–95 gate-level simulation, 95 protocol, 94–95 Core-level testbenches, 90 Core-level timing verification, 90–93 flow, 92 gate-level simulation in, 93 Core-level validation, 86–93 flow, 87 plan, 86–88 testbenches, 88–90 tools, 87–88 See also Design validation Core libraries, 21–22 defined, 21 LSI Logic, 21–22 Core models, 42–43 Cores analog, 72–78, 182–204 with boundary scan, 135–38 design methodology for, 33–55 DSP, 147 firm, 5, 43–47 hard, 5, 47–51 integration, 4, 113–15 I/Os, 42 with localized TAP controllers, 135, 138 local PLLs, 39 microprocessor, 105–12 non-TAP (NTC), 136 reuse, 33 soft, 5, 43–47 testability guidelines, 142–43 trade-offs, without boundary scan, 132–35 Core testing, 125–52, 252–53 access, 128 BIST, 144–47 control, 128 debug support, 150–52 embedded, 127 example, 147–50 generalized architecture, 133 IEEE P1500 and, 129–38 integration, 127 IP protection and, 138–42 isolation, 127, 128–29 microprocessor, 144–52 strategy, 127 See also Testing Core Test Language (CTL), 132, 135 core test development example, 136 Task Force, 135 Cosimulation, 97–100 debugging model, 99–100 diminishing bug rate, 102 distributed, 99 flow, 97, 98 models, 99 requirements, 97 Cosyma, 19–21 codesign flow, 20 defined, 19 Cx, 19–21 defined, 19 processes, 19–20 process partitions, 21 Dead cycles, 242–43 defined, 242 issues, 243 269 270 System-On-a-Chip: Design and Test Debugging cosimulation and, 99–100 HDL tool, 100 microprocessor core support, 150–52 Deliverables, 52–53 hard core, 53 soft core, 52 Design architecture, 35 ASIC vendor, codesign, 14–21 desktop, 3–4 entry, 23 forms, 3–4 for hard cores, 47–51 integrated, latch-based, 36 memory, 36–37 physical, 26, 40–42 for soft and firm cores, 43–47 synchronous, 36 verification, 13–14 vertical, 12 VLSI, 34, 35 Design flow, 13, 34–36 codesign, 15–18 core validation, 78 firm core, 43–45 memory compilers, 70 soft core, 43–45 VSI Alliance, 11 Design-for-Iddq-testing, 225–29 Design-for-reuse, 33 Design-for-test (DFT), 49, 126, 182 accessibility methods, 191 for analog cores, 191–200 Design issues, 8–14 design flow, 13 design verification, 13–14 layout, 14 portability methodology, processing and starting material difficulties, 8–9 technology optimization, 13 timing, Design reuse clear/set/reset signals, 40 clock distribution, 39–40 deliverable models, 42–43 general coding guidelines, 258–60 guidelines, 36–43 memory/mixed-signal design, 36–38 naming conventions, 257–58 on-chip buses, 38–39 physical design, 40–42 RTL guidelines for, 257–63 synchronous design, 36 test methodology for, 142–44 Design validation, 42, 85, 95–103, 252 core-level, 86–93 cosimulation, 97–100 defined, 85 emulation, 101 hardware prototypes, 101–3 simulation speed, 96–97 Desktop design, 3–4 Development process firm core, 45–46 hard cores, 49–51 soft core, 45–46 Differential nonlinearity (DNL), 74, 77, 183 dynamic, 186–87 static, 186 Digital-to-analog converters (DACs), 75–78, 181 accuracy, 77 AC parameters, 77–78 conversion time, 77 DC parameters, 76–77 differential nonlinearity (DNL), 77, 183 digital input voltages and currents, 77 dynamic linearity, 77 full-scale range, 76, 183 full-scale voltage, 76 functional parameters, 75–76 gain error, 76, 183 glitch impulse/energy, 77 integral nonlinearity (INL), 77, 183 intermodulation distortion (IM), 78, 184 LSB size, 77, 183 major transitions, 76 monotonicity, 77 Index offset error, 76, 182–83 offset voltage, 76 output noise level, 77 output rise/fall time, 78 output settling time, 77 output slew rate, 78 overvoltage recovery time, 77 parameters, 75–78, 185 power supply rejection ratio (PSRR), 77 propagation delay, 77 reference voltage, 76, 184 signal-to-noise and distortion (SINAD), 78, 184 signal-to-noise ratio (SNR), 78, 184 supply currents, 76 testing, 182–84 testing by on-chip microprocessor, 195–97 total harmonic distortion (THD), 78, 184 See also Analog-to-digital converters (ADCs) Documentation, hard core, 50 Double-bit error (DEC) codes, 175 Double-buffered memories (DBMs), 161–62 algorithms for, 162, 163 uses, 161–62 Drain-induced barrier lowering (DIBL), 222 DRAMs, 57 integrating, 58, 252 large embedded, 253 merged logic, 59, 60 parameters, 59 See also Memory DSP cores, 147 EDA environment complexity, 12 place and route flow, 12 synthesis flow, 1–12 tools and vendors, 23–27 Effective number of bits (ENOB), 75 Electronic Component Information Exchange (ECIX), Embedded memories, 57–72 circuit techniques, 61–66 compilers, 66–70 design methodology, 59–72 double-buffered (DBMs), 161–62 DRAMs, 57–59 motivations, 58 multiport, 161 PowerPC 603e G2, 112 production testing, 176–77 simulation models, 70–72 testing, 155–77 test methods, 162–71 See also Memory Emulation, 101 Error detecting and correcting codes (EDC) codes, 175 Fault models, 156–57 digital logic, 256 in Iddq test generators, 235 memory, 156–57 Faults addressing, 156 bit-pattern, 156–57 bridging, 156 cell coupling, 157 cell stuck-at, 156 data endurance, 157 data retention, 157 line stuck-at, 156 missing or extra bits, 156 open, 156 pattern-sensitive (PSF), 157 state transition, 157 timing, 157 undetected, 233 Firewire interface circuit, 80–81 ATE solution, 202 ATE test patterns, 203 common mode signaling, 81 differential signaling, 81 ideal test patterns, 202 illustrated, 82 testing, 201–4 Firm cores defined, design flow, 43–45 271 272 System-On-a-Chip: Design and Test Firm cores (continued) design process, 43–47 development process, 45–46 productization, 47 RTL guidelines, 46–47 RTL synthesis-based design illustration, 44 trade-offs, See also Cores Floor planning, 41 benefits of, 41 guidelines, 66, 67 Fly-by, 243–45 architecture of tester pin electronics, 244 benefits, 245 required tasks, 243–44 support, 244 See also production Testing Formal verification tools, 24 FPGAs drawbacks, 102 emulation systems, 101 uses, 102 Full-scale range (FSR), 72 Functional testbench, 89 Future scenarios, 254–55 Galloping diagonal/column (GALDIA/GALCOL) test algorithm, 158 Galloping pattern (GALPAT) test algorithm, 158, 159 Gate-induced drain leakage (GIDL), 222 Gate-level netlist reduction method, 141 Gate-level simulation, 91–93, 95 benefits, 93 core interface verification, 95 in timing verification, 93 Gate-oxide defects, 213–14 examples, 213 reliability, 214 types, 213 See also Physical defects G-bus, 114–15 GDSII, Hard cores clock and reset, 48 custom circuits, 48–49 defined, deliverables, 53 designing with, 53–54 design process, 47–51 design process illustration, 50 development process, 49–51 documentation, 50 porosity, pin placement, aspect ratio, 48 sign-off checklist, 51–52 test, 49 trade-offs, unique design issues, 47–49 Hard repair, 171–73 Hardware-software codesign See Codesign H-bus interface, 113–14 defined, 113 illustrated, 114 High-level synthesis, 143–44, 253 High-speed circuits, 79–81 IEEE 1394 serial bus PHY layer, 80–81 I/O, 81 Rambus ASIC cell, 79–80 Hitachi SH bus interface, 113–14 IBM processor local bus (PLB), 113, 114 Iddq testing, 207–35, 254 for bridging defects, 212–13 design for, 225–29 design rules, 230–31 difficulties in SoC, 219–25 effectiveness, 217–19 open defects and, 216 patterns effectiveness, 235 theory, 220 See also Testing Iddq test vector generation, 231–35 flow, 234 procedure vector generation for bridging, 233 procedure vector selection (A), 232–33 procedure vector selection (B), 233 tool characteristics, 231–32 user-defined constraints, 232 IEEE 1394 physical layer core, 80–81 serial bus/Firewire, testing, 201–4 Index IEEE P1149.4, 197–200 ABM, 198–99 ATAP, 198 current proposal, 198 defined, 197–98 structure, 198 test bus, 199 IEEE P1500, 129–38 control scan path, 134 cores with boundary scan, 135–38 cores without boundary scan, 132–35 Core Test Language (CTL), 132, 135 Core Test Scalable Architecture (CTAG), 132 defined, 129 principles, 129–32 Scalable Architecture Task Force, 130 wrapper, 130–31 wrapper interface, 131 Implementation verification, 85 Inputs/outputs (I/Os) definition of, 42 high-speed, 81 placement, 42 Integral nonlinearity (INL), 74, 77, 183 dynamic, 186–87 static, 186 Integrated design, Intel i860 microprocessor, Intermodulation distortion (IM), 75, 78, 184 Isolation, 127, 128–29 double, 129 method illustration, 130 objective, 128 single, 129 See also Core testing Latch-based design, 36 Layout, 14 Line stuck-at faults, 156 Lint tools, 262 Logic simulation, 23–24 Logic synthesis tools, 25 LPGAs, 102 March algorithm, 158–59 Media processors, 116–21 273 architecture functions, 116–17 architecture illustration, 116 arithmetic operations, 117 bit manipulation function, 116 components, 117–18 memory access, 117 real-time task switching, 117 Sony/Toshiba, 118–21 stream data I/O, 117 Memory application structures, 63 BISR, 253 cell structure, 61 circuit elements, 62 design, 36–37 design methodology, 57–72 embedded, 57–72 redundancy and repair, 171–75 transistor sizes and, 69 Memory BIST, 164–69, 253 cost, 167 deterministic testing, 167–68 illustrated, 168 methods, 165, 169 RAMBIST, 165, 166, 167 Memory compilers, 66–70, 112–13, 252 commercialized, 66 defined, 66 example, 68 flow of, 68, 70 transistor sizing and, 68–69 Memory testing, 155–77 algorithms, 157–60 application by direct access, 164 application by scan or collar register, 164 with ASIC functional test, 163 BIST, 164–69 comparison, 172 fault models, 156–57 methods, 162–71 with on-chip microprocessor, 169–71 summary, 171 Microprocessor cores, 105–12 AMD 486DX, 106, 108 ARM, 106, 107 characteristics, 106 274 System-On-a-Chip: Design and Test Microprocessor cores (continued) debug support, 150–52 for embedded applications, 105 NEC V830R/AV, 109–10 PowerPC 603e G2, 110–12 testing, 144–52 See also Cores Moore’s law, MSCAN, 158 Multi-DUT testing, 248–49 Multiport memories, 161 Multiprocessor architecture, 19 Naming convention, 257–58 NEC V830R/AV core, 109–10 Non-TAP cores (NTC), 136 On-chip buses (OCBs), 9, 38–39 role in SoC design, 38–39 VSI Alliance, 39 Open defects, 214–16 detection, 214 detection difficulty illustration, 216 examples, 215 Iddq testing and, 216 See also Physical defects Open faults, 156 Parallel test, 149 Pattern-sensitive faults (PSF), 157 Phase-locked loops (PLLs), 78–79 capture range, 78, 189 closed loop parameters, 78–79, 189 cores, 39 dynamic IDD, 191 hold range, 78 jitter, 79, 190–91 lock range, 78, 189 lock time, 78 natural frequency and damping factor, 190 open-loop parameters, 79 output duty cycle, 79 output frequency range, 79 phase detector gain factor, 79, 190 phase/frequency step response, 78, 189 phase transfer function, 79, 190 pull-in range, 78, 190 RAC, 200 static phase error, 79 testing, 188–91 VCO center frequency, 189 VCO gain, 190 VCO transfer function, 79, 189 Physical defects, 207–19 bridging (shorts), 208–13 gate-oxide, 213–14 open (breaks), 214–16 spot, 210–11 studies, 207–8 Physical design, 40–42 floor plan, 41 inputs/outputs, 42 parasitic extraction tools, 25 synthesis, 41 timing, 41–42 tools, 26 validation and test, 42 Pinnacles Component Information Standards (PCIS), PllBIST, 194–95 Portability methodology, Power analysis tools, 26 PowerPC 603e G2 core, 110–12 block diagram, 111 clocking and power buses, 110 embedded memories, 112 routing channels, 110 simulation and design data formats, 112 See also Microprocessor cores Power supply rejection ratio (PSRR), 77 sensitivity ratio (PSSR), 74 Processor local bus (PLB), 113, 114 controller arrangement, 113 defined, 113 illustrated, 114 Production testing, 239–49 at-speed, 241–46 flow, 239–41 of SoC with large embedded memory, 176–77 throughput and material handling, 246–49 See also Testing Index Production throughputs, 246–49 multi-DUT testing, 248–49 tester setup, 247–48 test logistics, 246–47 Productization defined, 47 soft/firm core, 47 Protocol verification, 94–95 RAMBIST architecture, 165, 166 controller, 165, 166 total area overhead, 167 See also Memory BIST Rambus memory technology, 79 signaling level (RSL) technology, 80 Rambus ASIC cell (RAC), 200–201 defined, 200 on-chip PLLs, 200 Redundancy analysis, 171, 174 Regression testbench, 88–89 Repair flowchart, 174 hard, 171–73 soft, 175 with/without impact, 173 Round-trip delay (RTD), 241–43 matching, during switching, 243 path, 241, 242 time, 242 RTL checks, 262–63 coding guidelines, 46–47, 257–63 coding style, 46 development for synthesis, 260–61 model, 49 netlist, 235 objective, 260 restricted rule set, 252 synthesis, 260–61 Sense amplifiers, 61–66 AC parameters, 64–66 bandwidth noise, 65 closed loop gain, 62 common mode input voltage range, 64 275 common mode rejection ratio (CMRR), 64 DC parameters, 62–64 differential mode input voltage range, 64 gross functional parameters, 61–62 input bias current, 64 input noise voltage density, 65 input offset current, 64 input offset current temperature sensitivity, 64 input offset voltage, 62 input offset voltage adjustment range, 62–63 input offset voltage temperature sensitivity, 62 input resistance, 64 low-frequency input noise density, 65 open-loop voltage gain, 64 output short-circuit current, 64 output voltage swing, 62 phase margin, 65 popcorn noise, 65 power supply rejection ratio (PSRR), 64 settling time, 64 signal-to-noise and distortion (SINAD), 66 signal-to-noise ratio (SNR), 65 slew rate (SR), 65 small-signal rise time, 64 supply currents, 61 total harmonic distortion (THD), 65 transient response overshoot, 65 unity gain bandwidth, 65 Serial test, 149 Set-top box, 121–22 Signal-to-noise and distortion (SINAD), 66, 75, 78, 184 Signal-to-noise ratio (SNR), 65, 75, 78, 184 Sign-off checklist, 51–52 contents, 51 hard core, 51–52 purpose, 51 Single-bit error correcting and double-bit error detecting (SEC-DED) codes, 175 Single processor architecture, 19 276 System-On-a-Chip: Design and Test Slew rate (SR), 65 Soft cores defined, deliverables, 52 design flow, 43–45 designing with, 54 design process, 43–47 development process, 45–46 productization, 47 RTL guidelines, 46–47 RTL synthesis-based design illustration, 44 trade-offs, See also cores Soft repair, 175 Sonics integration architecture, 115 Sony/Toshiba media processor, 118–21 architecture, 119 block diagrams, 119 clock tree, 120 defined, 118 vector processor units, 118 See also Media processors Specification verification, 85 Speed binning, 245–46 defined, 245 illustrated, 246 postpackage flow, 245 Spot defects, 210–11 Standards organizations, Web sites, 29 State transition faults, 157 Static timing analysis, 40, 41–42 logic simulation vs., 93 performance of, 91 repetition, 41 tools, 25, 92 Sub blocks integration of, 46 specifications, 46 testbenches, 89–90 Synchronous design, 36 Synthesis chip-level, 41 high-level, 143–44, 253 process, 41 RTL, 260–61 System integration, 53–55 designing with hard cores, 53–54 designing with soft cores, 54 system verification, 54–55 System-on-a-chip (SoC) architecture, 5–8 architecture illustration, defined, design issues, 8–14 design validation, 95–103 example illustrations, examples, 115–22 test issues, 126–27 System specification languages, 15 TAP controllers boundary-scan, 147 hierarchical, 139, 253 localized, 135, 138 Technology optimization, 13 Test, 42 cost projection, 177 first package level, 241 hard core, 49 high-level, synthesis, 143–44 interface controller (TIC), 149–50 logistics, 246–47 parallel, 149 reusability, 126 second package level, 241 serial, 149 SoC issues, 126–27 tools, 27 Testability core, 142–43 set-top box SoC, 121–22 Test algorithms, 157–60 checker pattern, 158 comparison, 160 for DBMs, 161–62, 163 effectiveness, 160 galloping diagonal/column (GALDIA/GALCOL), 158 galloping pattern (GALPAT), 158, 159 March, 158–59 MSCAN, 158 Testbenches, 88–90 for code coverage, 89 Index core-level, 90 development illustration, 91 functional, 89, 90 importance, 89 for random testing, 88 regression, 88–89 sub-block, 89–90 for verifying instructions, 88 for verifying transactions, 88 Tester setup, 247–48 Testing analog/mixed-signal cores, 181–204 at-speed, 241–46 digital logic core, 125–52, 252–53 embedded memories, 155–77 Iddq, 207–35, 254 microprocessor core, 144–52 multi-DUT, 248–49 on-chip microprocessor, 169–71, 195–97 production, 176–77, 239–49 random, 88 specific analog circuits, 200–204 wafer sort, 239–40 Timing faults, 157 issues, static, analysis, 25, 40, 41–42, 91–92 verification, 90–93 Tools, 23–27 ASIC emulation, 27 codesign, 18–21, 23 core-level validation, 87–88 design entry, 23 formal verification, 24 Lint, 262 logic simulation, 23–24 logic synthesis, 25 physical design, 26 physical design parasitic extraction, 25 277 power analysis, 26 static timing analysis, 25 test and testability, 27 Toshiba general-purpose bus, 114–15 Total harmonic distortion (THD), 65, 75, 78, 184 User-defined logic (UDL), 127 Validation See Design validation Verification, 252 core interface, 93–95 defined, 85 diminishing bug rate, 102 implementation, 85 protocol, 94–95 specification, 85 strategy, 86 system, 54–55 timing, 90–93 Verilint, 262–63 defined, 262 error situations, 263 warning situations, 262–63 Verilog/VHDL, 5, 12 memory models, 70 transforming timing information into, 71 Virtual Socket Interface (VSI) Alliance, design flow, 11 hierarchical bus architecture, 10 on-chip bus, 39 VLSI design, 34, 35 VSPEC, 34 Wafer sort testing, 239–40 Web pointers, 28–29 company sites, 28–29 guides, news, summaries, 28 standards organizations, 29 [...]... may be somewhat modified However, Figure 1.9 shows that simulation models are created at each step, analyzed and validated Table 1.1 Summary of System Specification Languages Language Concurrency Communication Timing Interface Note VHDL OK Inadequate Excellent Text IEEE standard SDL OK OK Inadequate Text/graphics ITU standard Java Excellent Excellent Inadequate — — C, C+ + N /A N /A N /A Text — SpecChart... StateChart Excellent Inadequate OK Graphics — PetriNet Excellent Inadequate Excellent Graphics — Esterel Inadequate Inadequate Excellent Text — 16 System- on- a- Chip: Design and Test System requirement specifications High-level algorithmic model HW/SW partitioning and task allocation Partitioning model Create simulation models, analyze and validate Scheduling model Communication model HW/SW interface... experience and a cost/performance trade-off Tools such as Forsight are helpful in this task The final step in partitioning Introduction 17 is to define the interface and protocols between hardware and software followed by the detailed specs on individual partitions of both software and hardware Once the hardware and software partitions have been determined, a behavioral model of the hardware is created together... Verification flow Creation flow System design Verification flow Bus functional verification Behavioral models Emulation model Eval test bench RTL functional verification System design Bus functional verification RTL SW drivers Functional test Test bench Floorplanning synthesis placement System modeling/ analysis Data sheet ISA model Bus functional models RTL design System requirement generation Synthesis script... definition Software specs Hardware specs Use case analysis Architecture design Subsystem Case design design Use case design Behavioral model Partitioning RTL Synthesis Hardware-software co-simulation/verification Figure 1.9 A general hardware–software codesign methodology Some form of validation and analysis is necessary at every step in order to reduce the risk of errors The design steps include partitioning,... document and specifications for an on- chip bus [12, 13] The objectives of the architecture and on- chip bus (OCB) specifications are to accelerate the mix -and- match capabilities of cores That is, in an SoC design with almost any on- chip bus, almost any virtual component interface (VCI) compliant core can be integrated The conceptual view of a VSI OCB-based SoC design is illustrated in Figure 1.6 [13] Conceptually,... specification and design of systems that include hardware and software components Hardware–software codesign is a very active research area At the present time a set of tools is required because most of the commercial codesign tools are primarily cosimulation engines that do not provide system- level timing, simulation, and verification Due to this lack of functionality in commercial tools, codesign... the initial design phase, they require continuous refinement as the design progresses As the high-level model begins to finalize, the system architect decides on the software and hardware partitions to determine what functions should be done by the hardware and what should be achieved by the software applications Partitioning the software and hardware subsystems is currently a manual process that requires... generation Both stimulus and peripheral models are removed for scheduling and partitioning Another input is a list of constraints and a user directives file that contains time constraints referring to labels in Cx processes as well as channel mapping directives, partitioning directives, and component selections The input description is translated into an extended syntax graph after some analysis of local... efforts are: • Pinnacles Component Information Standards (PCIS) by Reusable Application-Specific Intellectual Property Developers (RAPID) [8, 9]; • Electronic Component Information Exchange (ECIX) program by Silicon Integration Initiative (Si2) [10, 11]; and • Embedded core design and test specifications by Virtual Socket Interface (VSI) Alliance [12–16] The VSI Alliance has also developed an architecture ... community as a general publication With that thought, I contacted Artech House The editorial staff at Artech House had already been hearing and reading a lot about system- ona -chip and was very... LeapFrog(VHDL), Cobra (Verilog), Affirma NC Verilog, Affirma NC VHDL, Affirma Spectre (analog, 24 System- on- a- Chip: Design and Test mixed-signal), Affirma RF simulation and Affirma Verilog -A. .. simulation models are created at each step, analyzed and validated Table 1.1 Summary of System Specification Languages Language Concurrency Communication Timing Interface Note VHDL OK Inadequate