MIPS processor design 1 Introduction “The performance of software systems is dramatically affected by how well soft ware designers understand the basic hardware technologies at work in a system.” According to the book “Computer Organization Design” written by David A. Patterson and John L. Hennessy the hardware and behaviour of a micropro cessor is implemented in VHDL.
University of Ulster at Jordanstown University of Applied Sciences, Augsburg Master of Engineering VLSI Design Project Report Processor Implementation in VHDL According to Computer Organisation & Design by David A. Patterson and John L. Hennessy Author(s): M. Linder M. Schmid Supervisor(s): J. Färber A. Eder Submitted: 06/07/07 Document Revision History, Designers Document Revision History Rev. Date Author Description 0.1 15/05/2007 M. Schmid First draft release 0.2 15/05/2007 M. Linder Features of the project 0.3 29/05/2007 M. Linder Target Spec. (2.1, 2.2) 0.4 10/06/2007 M. Linder Target Spec. (2.3) 0.5 30/06/2007 M. Linder - include jump instruction to Target Spec. - Module Spec. of Control 0.6 02/07/2007 M. Linder Module Spec. of Data 0.6.1 02/07/2007 M. Schmid Module Spec. of ALU and Memory 0.6.2 03/07/2007 M. Schmid Design Tasks 0.7 04/07/2007 M. Linder - Module Spec. of Datapath - Synthesis Results - References 0.8 05/07/2007 M. Linder, M. Schmid - Synthesis Results - Source Code - Conclusion 1.0 05/07/2007 M. Linder, M. Schmid Final release Designer(s) M. Linder michael-linder@web.de M. Schmid martin-werner.schmid@gmx.de Contact Michael Linder Angerstraße 8a 86356 Neusäß, Germany Phone: +49 (0) 176 22 93 58 30 Mail: michael-linder@web.de Martin Schmid Fichtenstraße 2 86500 Kutzenhausen, Germany Phone: +49 (0) 160 92 94 91 54 Mail: martin-werner.schmid@gmx.de M. Linder, M. Schmid II Department of Electrical Engineering Contents Contents 1 Introduction 1 1.1 Starting from a Simple Implementation Scheme 1 1.2 Using Multicycle Implementations 2 1.3 Enhancing Performance with Pipelining 2 2 Target Specification 3 2.1 Building a Datapath 3 2.1.1 Major Components 3 2.1.2 Components for Arithmetic and Logic Functions 4 2.1.3 Load word (lw) and store word (sw) instructions 5 2.1.4 Branch on equal instruction 6 2.1.5 Jump Instruction 6 2.2 Simple Implementation Scheme 7 2.2.1 Creating a Single Datapath 7 2.2.2 ALU Control 8 2.2.3 Main Control 9 2.2.4 Disadvantages of a Single-Cycle Implementation 10 2.3 Multicycle Implementation 11 2.3.1 Additions and Changes in the Scheme 11 2.3.2 Execution of Instructions in Clock Cycles 14 2.3.3 Defining the Control by a Finite State Machine 18 3 Design Tasks 21 4 Module Specification 22 4.1 ALU 22 4.1.1 Functional Description 22 4.1.2 Block Diagram 23 4.1.3 Simulation Results 26 4.1.4 Design Files 26 4.2 Memory 27 4.2.1 Functional Description 27 4.2.2 Block Diagram 28 4.2.3 Simulation Results 28 4.2.4 Design Files 29 M. Linder, M. Schmid III Department of Electrical Engineering Contents 4.3 Control 30 4.3.1 Functional Description 30 4.3.2 State Diagram 31 4.3.3 Block Diagram 32 4.3.4 Simulation Results 33 4.3.5 Design Files 33 4.4 Data Path 34 4.4.1 Instruction Fetch 34 4.4.1.1 Functional Description 34 4.4.1.2 Block Diagram 34 4.4.1.3 Design Files 35 4.4.2 Instruction Decode 35 4.4.2.1 Functional Description 35 4.4.2.2 Block Diagram 35 4.4.2.3 Design Files 36 4.4.3 Execution 36 4.4.3.1 Functional Description 36 4.4.3.2 Block Diagram 37 4.4.3.3 Design Files 38 4.4.4 Memory Writeback 39 4.4.4.1 Functional Description 39 4.4.4.2 Block Diagram 40 4.4.4.3 Design Files 41 4.4.5 Data Path 42 4.4.5.1 Block Diagram 42 4.4.5.2 Design Files 42 4.5 Processor and Memroy 43 4.5.1 Functional Description 43 4.5.2 Block Diagram 43 4.5.3 Design Files 44 5 Synthesis Results 45 6 Results of Prototype Testing 47 6.1 Description 47 6.2 Simulation Result 49 7 Conclusion 50 7.1 Our own experiences 50 M. Linder, M. Schmid IV Department of Electrical Engineering Contents 7.2 Annotations to “Computer Organization & Design” [PaHe98] 50 7.3 Further work on the project 51 8 Appendix 52 8.1 Design files 52 8.1.1 Project Entities 52 8.1.2 Project Architectures 58 8.1.3 Package 79 8.1.4 Testbenches 80 8.2 References 91 M. Linder, M. Schmid V Department of Electrical Engineering Contents List of Figures Figure 1.1: Simple block diagram with datapaths [PaHe98] p. 352 1 Figure 1.2: Multicycle Datapath [PaHe98] p. 414 2 Figure 1.3: Pipelined Version of the Datapath [PaHe98], p. 452 2 Figure 2.1: Instruction Memory, Program Counter and Adder [PaHe98], p 344 3 Figure 2.2: Datapath for fetching instructions and incrementing the PC [PaHe98] p. 345 3 Figure 2.3: Register and ALU [PaHe98] p. 346 4 Figure 2.4: Datapath for R-type Instructions [PaHe98] p. 347 4 Figure 2.5: Data Memory and Sign extension unit [PaHe98] p. 348 5 Figure 2.6: Load or Store Word instruction field 5 Figure 2.7: Datapath for Load Word and Store Word [PaHe98] p. 348 5 Figure 2.8: Datapath for a branch instruction [PaHe98] p. 350 6 Figure 2.9: Completed Simple Datapath [PaHe98] p. 353 7 Figure 2.10: MIPS field 8 Figure 2.11: Table for ALU Control 8 Figure 2.12: Datapath with ALU Control Unit [PaHe98] p. 358 9 Figure 2.13: Meaning of the main control signals [PaHe98] p. 359 9 Figure 2.14: The simple datapath with the control unit [PaHe98] p. 360 10 Figure 2.15: Truth table of the main control unit [PaHe98] p. 361 10 Figure 2.16: Abstract view of a multicycle desing [PaHe98] p. 378 11 Figure 2.17: Complete Datapath for multicycle design [PaHe98] p. 383 13 Figure 2.18: Actions of 1-bit control signals [PaHe98] p. 384 14 Figure 2.19: Actions of 2-bit control signals [PaHe98] p. 384 14 Figure 2.20: Summary of the multicycle steps [PaHe98] p. 389 18 Figure 2.21: Complete finite state machine control [PaHe98] p. 396 19 Figure 2.22: Setting of Control Signals 20 Figure 4.1: ALU 1/3 23 Figure 4.2: ALU 2/3 24 Figure 4.3: ALU 3/3 25 Figure 4.4: Simulation Results of ALU 26 Figure 4.5: Memory 28 M. Linder, M. Schmid VI Department of Electrical Engineering Contents Figure 4.6: Simulation Results of Memory (registered outputs) 28 Figure 4.7: Simulation Results of Memory (unregistered outputs) 29 Figure 4.8: Control Finite State Machine 31 Figure 4.9: Control FSM 32 Figure 4.10: ALU Control 32 Figure 4.11: Control 33 Figure 4.12: Simulation Results of the Control FSM 33 Figure 4.13: Instruction Fetch 34 Figure 4.14: Instruction Decode 35 Figure 4.15: Execution 37 Figure 4.16: Memory Writeback 40 Figure 4.17: Processing Unit (Datapath & Controlpath) 43 Figure 4.18: Processing Unit & Memory 43 Figure 5.1: Analysis & Synthesis Summary 45 Figure 5.2: Analysis & Synthesis Settings 46 Figure 5.3: Compilation History 46 Figure 6.1: Simulation Results of MIPS and Memory 49 M. Linder, M. Schmid VII Department of Electrical Engineering Contents List of VHDL-Source VHDLSource 8.1: e_control_ControlFSM.vhd 52 VHDLSource 8.2: e_control_ALUControl.vhd 52 VHDLSource 8.3: e_control.vhd 52 VHDLSource 8.4: e_tempreg.vhd 53 VHDLSource 8.5: e_pc.vhd 53 VHDLSource 8.6: e_instreg.vhd 53 VHDLSource 8.7: e_regfile.vhd 54 VHDLSource 8.8: e_alu_vhd 54 VHDLSource 8.9: e_data_fetch.vhd 54 VHDLSource 8.10: e_data_decode.vhd 55 VHDLSource 8.11: e_data_execution.vhd 55 VHDLSource 8.12: e_data_memwriteback.vhd 56 VHDLSource 8.13: e_data.vhd 56 VHDLSource 8.14: e_ram.vhd 56 VHDLSource 8.15: e_memory.vhd 57 VHDLSource 8.16: e_mips.vhd 57 VHDLSource 8.17: e_procmem.vhd 57 VHDLSource 8.18: a_control_ControlFSM.vhd 60 VHDLSource 8.19: a_control_ALUControl.vhd 61 VHDLSource 8.20: a_control.vhd 62 VHDLSource 8.21: a_tempreg_behave.vhd 63 VHDLSource 8.22: a_pc_behave.vhd 63 VHDLSource 8.23: a_instreg_behave.vhd 64 VHDLSource 8.24: a_regfile_behave.vhd 64 VHDLSource 8.25: a_alu_behave.vhd 65 VHDLSource 8.26: a_data_fetch.vhd 67 VHDLSource 8.27: a_data_decode.vhd 69 VHDLSource 8.28: a_data_execution.vhd 69 VHDLSource 8.29: a_data_memwriteback.vhd 70 VHDLSource 8.30: a_data.vhd 73 VHDLSource 8.31: a_ram_rtl.vhd 73 M. Linder, M. Schmid VIII Department of Electrical Engineering Contents VHDLSource 8.32: a_memory_behave.vhd 75 VHDLSource 8.33: a_mips.vhd 77 VHDLSource 8.34: a_procmem.vhd 78 VHDLSource 8.35: p_procmem_definitions.vhd 79 VHDLSource 8.36: t_alu_fileio.vhd 83 VHDLSource 8.37: t_memory.vhd 86 VHDLSource 8.38: t_procmem.vhd 87 M. Linder, M. Schmid IX Department of Electrical Engineering [...]... how well software designers understand the basic hardware technologies at work in a system.” According to the book “Computer Organization & Design written by David A Patterson and John L Hennessy the hardware and behaviour of a microprocessor is implemented in VHDL 1.1 Starting from a Simple Implementation Scheme In the first section starting from a simple implementation scheme of a MIPS subset the... Linder, M Schmid, 07/07 3 Design Tasks Department of Electrical Engineering 3 Design Tasks • Block Diagram of first hierarchy levels • Register Transfer Level Models implemented in pure VHDL • VHDL Testbench of important RTL Models • Implementation in Altera Target Technology • Prototype Testing • Simulation Tool: ModelSim • Synthesis Tool: Altera Quartus • Milestone Presentations • Design Project Report... Linder, M Schmid, 07/07 7 2.2 ALU Control Department of Electrical Engineering 2.2.2 ALU Control The MIPS field that contains the information about the instruction has the following structure: op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits Desired ALU action ALU control input Figure 2.10: MIPS field The meaning of the fields are: • op: basic operation • rs: first register source • rt:... adder that computes the value of PC + 4 The PC is replaced by the output of the adder that computes the branch target MemRead None Data memory contents designated by the address input are put on the Read data output MemWrite None Data memory contents designated by the address input are replaced by the value on the Write data input MemtoReg The value fed to the register Write data input comes from the... 1 0 0 0 beq X 0 X 0 0 0 1 0 1 Instruction R-format Figure 2.15: Truth table of the main control unit [PaHe98] p 361 2.2.4 Disadvantages of a Single-Cycle Implementation In modern designs a single cycle implementation of a processor is not used, because it is inefficient A clock cycle must have the same length for every instruction and therefore it is determined by the longest possible path Almost this... be used more than once in a instruction, so that the number of functional units can be reduced The major advantage of a multicycle design is the ability to share functional units within an execution 2.3.1 Additions and Changes in the Scheme Figure 2.16 shows a abstract design of a multicycle datapath Figure 2.16: Abstract view of a multicycle desing [PaHe98] p 378 Comparing to the single-cycle datapath... implementation is not likely to be very good the processor s speed is improved by using multicycle implementations Then, instructions are allowed to take different numbers of clock cycles and functional units can be shared within the execution of single instructions 1.3 Enhancing Performance with Pipelining In order to enhance the performance and to get very fast processors another implementation technique... Simulation Tool: ModelSim • Synthesis Tool: Altera Quartus • Milestone Presentations • Design Project Report in OpenOffice Document Format • Design Directory Structure is mandatory according to the following table: Object Description toplevel Root directory for a VHDL design project toplevel/src directory for VHDL source code toplevel/work directory for VHDL working library, contains compiled object code... this directory toplevel/pnr data produced after a place&route run can be found in this directory toplevel/scripts scriptfiles for automated batch processing of the design steps should be placed here toplevel/log log files of the different design steps toplevel/doc directory for project documentation, data sheets, etc M Linder, M Schmid, 07/07 21 4 Module Specification Department of Electrical Engineering... as the last two bits 6 M Linder, M Schmid, 07/07 2.2 Simple Implementation Scheme Department of Electrical Engineering 2.2 Simple Implementation Scheme The simplest possible implementation of the MISP Processor contains the datapath segments explained above added by the required control lines 2.2.1 Creating a Single Datapath The simplest datapath might attempt to execute all instructions in one clock