Altera DE2 Board DE2 Development and Education Board User Manual pdf

DE2 Package

Package Contents

Figure 1.1 shows a photograph of the DE2 package

Figure 1.1 The DE2 package contents

• USB Cable for FPGA programming and control

• CD-ROM containing the DE2 documentation and supporting materials, including the User Manual, the Control Panel utility, reference designs and demonstrations, device datasheets, tutorials, and a set of laboratory exercises

• CD-ROMs containing Altera’s Quartus ® II Web Edition and the Nios ® II Embedded Design Suit Evaluation Edition software

This package includes six silicone rubber covers designed for the DE2 board stands, along with extender pins that simplify the probing process with testing equipment on the board’s I/O expansion headers.

• Clear plastic cover for the board

• 9V DC wall-mount power supply

The DE2 Board Assembly

To assemble the included stands for the DE2 board:

• Assemble a rubber (silicon) cover, as shown in Figure 1.2, for each of the six copper stands on the DE2 board

• The clear plastic cover provides extra protection, and is mounted over the top of the board by using additional stands and screws

Figure 1.2 The feet for the DE2 board

Getting Help

Here are the addresses where you can get help if you encounter problems:

Jhubei City, HsinChu County, Taiwan, 302

Email: DE2support@archescomputing.com

A dedicated Bulletin Board System (BBS) Forum for the DE2 board has been established at the link provided below This Forum serves as a comprehensive resource for information related to the DE2 board, enabling users to ask questions and share design examples effectively.

• BBS forum: http://www.terasic.com/english/discuss.htm

Altera DE2 Board

Layout and Components

A photograph of the DE2 board is shown in Figure 2.1 It depicts the layout of the board and indicates the location of the connectors and key components

The DE2 board has many features that allow the user to implement a wide range of designed circuits, from simple circuits to various multimedia projects

The following hardware is provided on the DE2 board:

• Altera Cyclone ® II 2C35 FPGA device

• Altera Serial Configuration device - EPCS16

• USB Blaster (on board) for programming and user API control; both JTAG and Active Serial (AS) programming modes are supported

• 4-Mbyte Flash memory (1 Mbyte on some boards)

• 50-MHz oscillator and 27-MHz oscillator for clock sources

• 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks

• VGA DAC (10-bit high-speed triple DACs) with VGA-out connector

• TV Decoder (NTSC/PAL) and TV-in connector

• USB Host/Slave Controller with USB type A and type B connectors

• RS-232 transceiver and 9-pin connector

• Two 40-pin Expansion Headers with diode protection

The DE2 board not only boasts impressive hardware features but also includes software support for standard I/O interfaces and a control panel for easy access to its various components Additionally, it comes with software demonstrations that showcase the board's advanced capabilities.

To effectively utilize the DE2 board, users must be proficient in Quartus II software, which can be learned through the tutorial "Getting Started with Altera’s DE2."

The Board and Quartus II Introduction offers three versions tailored to different design entry methods: Verilog, VHDL, and schematic entry These tutorials can be found in the designated directory.

DE2_tutorials on the DE2 System CD-ROM that accompanies the DE2 board and can also be found on Altera’s DE2 web pages.

Block Diagram of the DE2 Board

The DE2 board's block diagram, illustrated in Figure 2.2, showcases its design, which prioritizes user flexibility by routing all connections through the Cyclone II FPGA device This configuration allows users to customize the FPGA for any desired system design, enhancing adaptability and functionality.

Figure 2.2 Block diagram of the DE2 board

Following is more detailed information about the blocks in Figure 2.2:

Serial Configuration device and USB Blaster circuit

• Altera’s EPCS16 Serial Configuration device

• On-board USB Blaster for programming and user API control

• JTAG and AS programming modes are supported

• 512-Kbyte Static RAM memory chip

• Accessible as memory for the Nios II processor and by the DE2 Control Panel

• 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip

• 4-Mbyte NOR Flash memory (1 Mbyte on some boards)

• Provides SPI mode for SD Card access

• Accessible as memory for the Nios II processor with the DE2 SD Card Driver

• Debounced by a Schmitt trigger circuit

• Normally high; generates one active-low pulse when the switch is pressed

• 18 toggle switches for user inputs

• A switch causes logic 0 when in the DOWN (closest to the edge of the DE2 board) position and logic 1 when in the UP position

• Wolfson WM8731 24-bit sigma-delta audio CODEC

• Line-level input, line-level output, and microphone input jacks

• Applications for MP3 players and recorders, PDAs, smart phones, voice recorders, etc

• Uses the ADV7123 240-MHz triple 10-bit high-speed video DAC

• With 15-pin high-density D-sub connector

• Supports up to 1600 x 1200 at 100-Hz refresh rate

• Can be used with the Cyclone II FPGA to implement a high-performance TV Encoder

NTSC/PAL TV decoder circuit

• Uses ADV7181B Multi-format SDTV Video Decoder

• Integrates three 54-MHz 9-bit ADCs

• Clocked from a single 27-MHz oscillator input

• Supports Composite Video (CVBS) RCA jack input

• Supports digital output formats (8-bit/16-bit): ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

• Applications: DVD recorders, LCD TV, Set-top boxes, Digital TV, Portable video devices

• Integrated MAC and PHY with a general processor interface

• Supports 100Base-T and 10Base-T applications

• Supports full-duplex operation at 10 Mb/s and 100 Mb/s, with auto-MDIX

• Fully compliant with the IEEE 802.3u Specification

• Supports IP/TCP/UDP checksum generation and checking

• Supports back-pressure mode for half-duplex mode flow control

• Complies fully with Universal Serial Bus Specification Rev 2.0

• Supports data transfer at full-speed and low-speed

• Supports both USB host and device

• Two USB ports (one type A for a host and one type B for a device)

• Provides a high-speed parallel interface to most available processors; supports Nios II with a Terasic driver

• Supports Programmed I/O (PIO) and Direct Memory Access (DMA)

• DB-9 serial connector for the RS-232 port

• PS/2 connector for connecting a PS2 mouse or keyboard to the DE2 board

• 72 Cyclone II I/O pins, as well as 8 power and ground lines, are brought out to two 40-pin expansion connectors

• 40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives

• Diode and resistor protection is provided

Power-up the DE2 Board

The DE2 board is equipped with a preloaded configuration bit stream that showcases its features and enables users to quickly verify its functionality To power up the board, follow the designated steps.

1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 board For communication between the host and the DE2 board, it is necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer, it can be installed as explained in the tutorial Getting Started with Altera's

DE2 Board This tutorial is available on the DE2 System CD-ROM and from the Altera

2 Connect the 9V adapter to the DE2 board

3 Connect a VGA monitor to the VGA port on the DE2 board

4 Connect your headset to the Line-out audio port on the DE2 board

5 Turn the RUN/PROG switch on the left edge of the DE2 board to RUN position; the PROG position is used only for the AS Mode programming

6 Turn the power on by pressing the ON/OFF switch on the DE2 board

At this point you should observe the following:

• All user LEDs are flashing

• All 7-segment displays are cycling through the numbers 0 to F

• The LCD display shows Welcome to the Altera DE2 Board

• The VGA monitor displays the image shown in Figure 2.3

• Set the toggle switch SW17 to the DOWN position; you should hear a 1-kHz sound

To play music through the DE2 board, set the SW17 toggle switch to the UP position and connect your audio player's output to the Line-in connector You should hear the audio, whether it's from an MP3 player, PC, iPod, or similar device, through your headset.

• You can also connect a microphone to the Microphone-in connector on the DE2 board; your voice will be mixed with the music played from the audio player

Figure 2.3 The default VGA output pattern.

DE2 Control Panel

Control Panel Setup

To launch the Control Panel application, you must first set up a specific circuit within the Cyclone II FPGA by downloading the configuration file DE2_USB_API.sof Detailed instructions for the downloading process can be found in Section 4.1.

To successfully operate the DE2 board, you need to run the DE2_control_panel.exe program on your host computer, in addition to using the DE2_USB_API.sof file Both files can be found on the DE2 System CD-ROM in the DE2_control_panel directory, although they may already be installed in a different location on your computer.

To activate the Control Panel, perform the following steps:

1 Connect the supplied USB cable to the USB Blaster port, connect the 9V power supply, and turn the power switch ON

2 Set the RUN/PROG switch to the RUN position

3 Start the Quartus II software

4 Select Tools > Programmer to reach the window in Figure 3.1 Click on Add File and in the pop-up window that appears select the DE2_USB_API.sof file Next, click on the

Program/Configure box which results in the image displayed in the figure Now, click Start to download the configuration file into the FPGA

5 Start the executable DE2_control_panel.exe on the host computer The Control Panel user interface shown in Figure 3.2 will appear

6 Open the USB port by clicking Open > Open USB Port 0 The DE2 Control Panel application will list all the USB ports that connect to DE2 boards The DE2 Control Panel can control up to 4 DE2 boards using the USB links The Control Panel will occupy the USB port until you close that port; you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port

7 The Control Panel is now ready for use; experiment by setting the value of some 7-segment display and observing the result on the DE2 board

Figure 3.1 Quartus II Programmer window

Figure 3.2 The DE2 Control Panel

The DE2 Control Panel, as depicted in Figure 3.3, features an IP implemented in the FPGA device that executes control functions This IP communicates with the Control Panel window on the host computer through the USB Blaster link, allowing users to issue commands via a graphical interface The IP efficiently manages all requests and facilitates data transfers between the computer and the DE2 board.

Figure 3.3 The DE2 Control Panel concept

The DE2 Control Panel enables users to modify values on 7-segment displays, activate LEDs, interact with a PS/2 keyboard, and read/write data to SRAM, Flash Memory, and SDRAM Additionally, it supports loading image patterns for VGA output and playing music through an audio DAC Its capability to read and write bytes or entire files from Flash Memory facilitates the development of multimedia applications, such as Flash Audio Players and Flash Picture Viewers, without the need for a Flash Memory Programmer.

Controlling the LEDs, 7-Segment Displays and LCD Display

A simple function of the Control Panel is to allow setting the values displayed on LEDs, 7-segment displays, and the LCD character display

In the interface illustrated in Figure 3.2, users can input values for the 7-segment displays, referred to as HEX7-0, into designated fields and confirm their entry by clicking the Set button Additionally, a keyboard connected to the PS/2 port allows users to type text for display on the LCD screen.

To control the LED and LCD settings, navigate to the LED & LCD tab as shown in Figure 3.4 You can activate individual LEDs by selecting them and pressing the Set button Additionally, to display text on the LCD, simply type your message in the LCD box and press the appropriate Set button.

While setting arbitrary values in basic display devices is generally unnecessary for standard design tasks, it offers users an effective way to verify proper functionality, especially when troubleshooting potential malfunctions.

Figure 3.4 Controlling LEDs and the LCD display.

SDRAM/SRAM Controller and Programmer

The Control Panel allows users to read and write data to the SDRAM and SRAM chips on the DE2 board To access the SDRAM, simply click on the SDRAM tab, which will open the corresponding window as shown in Figure 3.5 The method for accessing SRAM follows the same procedure.

To write a 16-bit word into SDRAM, enter the target address and specify the data, then press the Write button To read the contents of the location, simply press the Read button For example, writing the hexadecimal value 6CA into location 200 and subsequently reading that location is illustrated in Figure 3.5.

The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows:

1 Specify the starting address in the Address box

2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded, then a checkmark may be placed in the File Length box instead of giving the number of bytes

3 To initiate the writing of data, click on the Write a File to SDRAM button

4 When the Control Panel responds with the standard Windows dialog box asking for the source file, specify the desired file in the usual manner

The Control Panel allows for the loading of files with a hex extension, which are ASCII text files that define memory values by using ASCII characters to represent hexadecimal values.

0123456789ABCDEF defines four 16-bit values: 0123, 4567, 89AB, CDEF These values will be loaded consecutively into the memory

The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows:

1 Specify the starting address in the Address box

2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied (which involves all 8 Mbytes), then place a checkmark in the Entire SDRAM box

3 Press Load SDRAM Content to a File button

4 When the Control Panel responds with the standard Windows dialog box asking for the destination file, specify the desired file in the usual manner

Flash Memory Programmer

The Control Panel can be used to write/read data to/from the Flash memory chip on the DE2 board

It can be used to:

• Erase the entire Flash memory

• Write one byte to the memory

• Read one byte from the memory

• Write a binary file to the memory

• Load the contents of the Flash memory into a file

Note the following characteristics of the Flash memory:

• The Flash memory chip is organized as 4 M (or 1 M on some boards) x 8 bits

• You must erase the entire Flash memory before you can write into it (Be aware that the number of times a Flash memory can be erased is limited.)

• The time required to erase the entire Flash memory is about 20 seconds Do not close the DE2 Control Panel in the middle of the operation

To open the Flash memory control window, shown in Figure 3.6, select the FLASH tab in the Control Panel

Figure 3.6 Flash memory control window

A byte of data can be written into a random location on the Flash chip as follows:

1 Click on the Chip Erase button The button and the window frame title will prompt you to wait until the operation is finished, which takes about 20 seconds

2 Enter the desired address into the Address box and the data byte into the wDATA box Then, click on the Write button

To read a byte of data from a random location, enter the address of the location and click on the

Read button The rDATA box will display the data read back from the address specified

The Sequential Write function is used to load a file into the Flash chip as follows:

1 Specify the starting address and the length of data (in bytes) to be written into the Flash memory You can click on the File Length checkbox to indicate that you want to load the entire file

2 Click on the Write a File to Flash button to activate the writing process

3 When the Control Panel responds with the standard Windows dialog box asking for the source file, specify the desired file in the usual manner

The Sequential Read function is used to read the data stored in the Flash memory and write this data into a file as follows:

1 Specify the starting address and the length of data (in bytes) to be read from the Flash memory You can click on the Entire Flash checkbox to indicate that you want to copy the entire contents of the Flash memory into a specified file

2 Click on the Load Flash Content to a File button to activate the reading process

3 When the Control Panel responds with the standard Windows dialog box asking for the destination file, specify the desired file in the usual manner.

Overall Structure of the DE2 Control Panel

The DE2 Control Panel interacts with a circuit implemented in the Cyclone II FPGA, allowing users to modify its functionality through Verilog code This code can be found in the DE2_demonstrations directory on the DE2 System CD-ROM.

To operate the Control Panel, users must first complete the setup process outlined in Section 3.1 The Control Panel's structure is illustrated in Figure 3.7, where each input/output device is managed by a controller within the FPGA chip Communication with the PC occurs through the USB Blaster link, while a Command Controller circuit interprets commands from the PC to execute the necessary actions Additionally, the SDRAM, SRAM, and Flash Memory controllers feature three user-selectable asynchronous ports, alongside a Host port that connects to the Command Controller The VGA DAC Controller's connection to the FPGA memory enables the display of a default image stored in an M4K block within the Cyclone.

II chip The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz

We offer an integrated control environment that allows users to easily implement and test their Verilog IP cores without the need for complex API or host control software, as well as memory controllers for SRAM, SDRAM, and Flash This environment includes a C++ software controller, a USB command controller, and a multi-port memory controller.

Figure 3.7 The DE2 Control Panel block diagram

Users can connect custom-designed circuits to the User Ports of the SRAM/SDRAM/Flash controller, allowing them to download binary data into the memory After transferring data to the SDRAM/Flash, users can configure the memory controllers to enable their circuits to read and write to the SDRAM/Flash through the connected User Ports.

TOOLS – Multi-Port SRAM/SDRAM/Flash Controller

The TOOLS page in the Control Panel GUI enables users to select User Ports for various applications This article demonstrates a typical implementation by showcasing a Flash Music Player, where music data is stored in Flash memory User Port 1 of the Flash Controller transmits the music data to the Audio DAC Controller, facilitating audio output through the audio jack.

You can implement this application as follows:

1 Erase the Flash memory (as explained in Section 3.4) Then, write a music file into the Flash memory You can use the file music.wav in the directory DE2_demonstrations\music on the DE2 System CD-ROM

2 In the DE2 Control Panel, select the TOOLS tab to reach the window in Figure 3.8

Figure 3.8 TOOLS window of the DE2 Control Panel

3 Select the Asynchronous 1 port for the Flash Multiplexer and then click on the Configure button to activate the port You need to click the Configure button to enable the connection from the Flash Memory to the Asynchronous Port 1 of the Flash Controller (indicated in Figure 3.7)

4 Set toggle switches SW1 and SW0 to OFF (DOWN position) and ON (UP position), respectively

5 Plug your headset or a speaker into the audio output jack and you should hear the music played from the Audio DAC circuit

6 Note that the Asynchronous Port 1 is connected to the Audio DAC part, as shown in Figure 3.7 Once you selected Asynchronous Port 1 and clicked the Configure button, the Audio DAC Controller will communicate with the Flash memory directly In our example, the

AUDIO_DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip.

VGA Display Control

The Control Panel includes a tool linked to an IP address that enables users to display images through the VGA output port This guide demonstrates how to display a default image on a VGA monitor by following specific steps.

• Select the VGA tab in the Control Panel to reach the window in Figure 3.9

Figure 3.9 Displayed image and the cursor controlled by the scroll bars

• Make sure that the checkboxes Default Image and Cursor Enable are checked

To connect a VGA monitor to the DE2 board, you will see the default image displayed on the screen, as shown in Figure 3.9 This image features a cursor that can be navigated using the X/Y-axes scroll bars available on the DE2 Control Panel.

The image depicted in Figure 3.9 is stored within an M4K memory block of the Cyclone II FPGA During the initial configuration stage of the default bit stream, it is loaded into the M4K block using the MIF/Hex (Intel) format.

We will next describe how you can display other images and use your own images to generate the binary data patterns that can be displayed on the VGA monitor

Another image is provided in the file picture.dat in the folder DE2_demonstrations\pictures on the

DE2 System CD-ROM You can display this image as follows:

• Select the SRAM page of the Control Panel and load the file picture.dat into the SRAM

• Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3.10 Click on the Configure button to activate the multi-port setup

Figure 3.10 Use the Asynchronous Port 1 to access the image data in the SRAM

• The FPGA is now configured as indicated in Figure 3.11

• Select the VGA page and deselect the checkbox Default Image

• The VGA monitor should display the picture.dat image from the SRAM, as depicted in Figure 3.12 You can turn off the cursor by deselecting the Cursor Enable checkbox

Figure 3.11 Multi-Port Controller configured to display an image from the SRAM

To display an image file using the Cyclone II chip, you can load it into the SRAM chip or an M4K memory block This process involves generating a bitmap file, which is essential for proper image rendering.

1 Load the desired image into an image processing tool, such as Corel PhotoPaint

2 Resample the original image to have a 640 x 480 resolution Save the modified image in the Windows Bitmap format

3 Execute DE2_control_panel\ImgConv.exe, an image conversion tool developed for the

DE2 board, to reach the window in Figure 3.13

4 Click on the Open Bitmap button and select the 640 x 480 Grayscale photo for conversion

5 When the processing of the file is completed, click on the Save Raw Data button and a file named Raw_Data_Gray.dat will be generated and stored in the same directory as the original image file You can change the file name prefix from Raw_Data to another name by changing the File Name field in the displayed window

6 Raw_Data_Gray.dat is the raw data that can be downloaded directly into the SRAM on the

DE2 board and displayed on the VGA monitor using the VGA controller IP described in the DE2_USB_API project

7 The ImgConv tool will also generate Raw_Data_BW.dat (and its corresponding TXT format) for the black and white version of the image – the threshold for judging black or white level is defined in the BW Threshold

Figure 3.13 The image converter window

Color Picture R/G/B N/A Raw_Data_Gray

BW Threshold Raw_Data_BW +

Raw_Data_BW.txt Grayscale

N/A BW Threshold Raw_Data_BW +

Raw_Data_BW.txt Note: Raw_Data_BW.txt is used to fill in the MIF/Intel Hex format for M4K SRAM

Using the DE2 Board

Configuring the Cyclone II FPGA

To download a circuit from a host computer to the DE2 board, refer to the Quartus II Introduction tutorial located in the DE2_tutorials folder on the DE2.

The System CD-ROM is accessible on the Altera DE2 website, where users are advised to first read the tutorial, using the information provided below as a concise reference guide.

The DE2 board features a serial EEPROM chip that retains configuration data for the Cyclone II FPGA, which is automatically loaded into the FPGA upon powering the board Users can reprogram the FPGA and modify the non-volatile data in the EEPROM chip at any time using Quartus II software Both programming methods are detailed in the following sections.

1 JTAG programming: In this method of programming, named after the IEEE standards Joint Test Action Group, the configuration bit stream is downloaded directly into the Cyclone II

FPGA The FPGA will retain this configuration as long as power is applied to the board; the configuration is lost when the power is turned off

2 AS programming: In this method, called Active Serial programming, the configuration bit stream is downloaded into the Altera EPCS16 serial EEPROM chip It provides non-volatile storage of the bit stream, so that the information is retained even when the power supply to the DE2 board is turned off When the board's power is turned on, the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA

This article outlines the steps for performing JTAG and AS programming on the DE2 board, which connects to a host computer via USB The board is recognized by the computer as an Altera USB Blaster device For successful communication, users must install the necessary software device driver, detailed in the tutorial "Getting Started with Altera's DE2 Board," available on the DE2 System CD-ROM and Altera's DE2 web pages.

Configuring the FPGA in JTAG Mode

Figure 4.1 illustrates the JTAG configuration setup To download a configuration bit stream into the

Cyclone II FPGA, perform the following steps:

• Ensure that power is applied to the DE2 board

• Connect the supplied USB cable to the USB Blaster port on the DE2 board (see Figure 2.1)

• Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side of the board) to the RUN position

• The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension

Figure 4.1 The JTAG configuration scheme

Configuring the EPCS16 in AS Mode

Figure 4.2 illustrates the AS configuration set up To download a configuration bit stream into the

EPCS16 serial EEPROM device, perform the following steps:

• Ensure that power is applied to the DE2 board

• Connect the supplied USB cable to the USB Blaster port on the DE2 board (see Figure 2.1)

• Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side of the board) to the PROG position

• The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension

After completing the programming operation, switch the RUN/PROG toggle back to the RUN position Then, reset the board by turning the power switch off and on again to load the new configuration data from the EPCS16 device into the FPGA chip.

Figure 4.2 The AS configuration scheme

The USB Blaster port on the DE2 board not only facilitates JTAG and AS programming but also enables remote control of various board features from a host computer For comprehensive details on utilizing the USB Blaster port for this purpose, refer to Chapter 3.

Using the LEDs and Switches

The DE2 board features four pushbutton switches, each debounced with a Schmitt Trigger circuit, ensuring reliable performance as clock or reset inputs The outputs, labeled KEY0 to KEY3, connect directly to the Cyclone II FPGA When unpressed, each switch outputs a high logic level of 3.3 volts, while pressing the switch results in a low logic level of 0 volts This design enhances the switches' functionality in various circuit applications.

The DE2 board features 18 toggle switches that serve as level-sensitive data inputs to a circuit These non-debounced switches connect directly to pins on the Cyclone II FPGA When a switch is in the DOWN position, it outputs a low logic level of 0 volts, while the UP position delivers a high logic level of 3.3 volts.

There are 27 user-controllable LEDs on the DE2 board Eighteen red LEDs are situated above the

The system features 18 toggle switches and eight green LEDs positioned above the pushbutton switches, with an additional green LED located between the 7-segment displays Each LED is controlled directly by a pin on the Cyclone II FPGA; setting the pin to a high logic level activates the LED, while a low logic level deactivates it Schematic diagrams illustrating the pushbutton and toggle switch connections are provided in Figure 4.4, and the LED circuitry is detailed in Figure 4.5.

The pin names associated with the toggle switches on the Cyclone II FPGA are outlined in Table 4.1, while Tables 4.2 and 4.3 provide details on the pins connected to the pushbutton switches and LEDs, respectively.

Figure 4.4 Schematic diagram of the pushbutton and toggle switches

Figure 4.5 Schematic diagram of the LEDs

Signal Name FPGA Pin No Description

SW[3] PIN_AE14 Toggle Switch[3]

SW[4] PIN_AF14 Toggle Switch[4]

SW[5] PIN_AD13 Toggle Switch[5]

SW[6] PIN_AC13 Toggle Switch[6]

Table 4.1 Pin assignments for the toggle switches

Table 4.2 Pin assignments for the pushbutton switches

LEDR[0] PIN_AE23 LED Red[0]

LEDR[1] PIN_AF23 LED Red[1]

LEDR[2] PIN_AB21 LED Red[2]

LEDR[3] PIN_AC22 LED Red[3]

LEDR[4] PIN_AD22 LED Red[4]

LEDR[8] PIN_AA14 LED Red[8]

LEDR[10] PIN_AA13 LED Red[10]

LEDR[14] PIN_AF13 LED Red[14]

LEDG[0] PIN_AE22 LED Green[0]

LEDG[1] PIN_AF22 LED Green[1]

LEDG[6] PIN_AA20 LED Green[6]

Table 4.3 Pin assignments for the LEDs

Using the 7-segment Displays

The DE2 Board features eight 7-segment displays organized into two pairs and one group of four, designed to showcase numbers in varying sizes According to the schematic in Figure 4.6, the seven segments connect to pins on the Cyclone II FPGA, where a low logic level activates a segment, while a high logic level deactivates it.

Each segment of a 7-segment display is labeled with an index ranging from 0 to 6, as illustrated in Figure 4.7 It is important to note that the dot in each display is not connected and is therefore unusable Additionally, Table 4.4 details the assignments of FPGA pins corresponding to the 7-segment displays.

Figure 4.6 Schematic diagram of the 7-segment displays

Figure 4.7 Position and index of each segment in a 7-segment display

HEX0[0] PIN_AF10 Seven Segment Digit 0[0]

HEX0[1] PIN_AB12 Seven Segment Digit 0[1]

HEX0[2] PIN_AC12 Seven Segment Digit 0[2]

HEX0[3] PIN_AD11 Seven Segment Digit 0[3]

HEX0[4] PIN_AE11 Seven Segment Digit 0[4]

HEX0[5] PIN_V14 Seven Segment Digit 0[5]

HEX1[2] PIN_W21 Seven Segment Digit 1[2]

HEX1[3] PIN_Y22 Seven Segment Digit 1[3]

HEX1[4] PIN_AA24 Seven Segment Digit 1[4]

HEX3[5] PIN_U22 Seven Segment Digit 3[5]

HEX3[6] PIN_W24 Seven Segment Digit 3[6]

HEX4[3] PIN_T4 Seven Segment Digit 4[3]

HEX4[4] PIN_R7 Seven Segment Digit 4[4]

HEX5[1] PIN_P6 Seven Segment Digit 5[1]

HEX6[3] PIN_M2 Seven Segment Digit 6[3]

HEX7[0] PIN_L3 Seven Segment Digit 7[0]

HEX7[6] PIN_N9 Seven Segment Digit 7[6]

Table 4.4 Pin assignments for the 7-segment displays.

Clock Inputs

The DE2 board features dual oscillators generating clock signals of 27 MHz and 50 MHz, along with an SMA connector for connecting an external clock source For a detailed view, refer to the schematic of the clock circuitry in Figure 4.8 and the corresponding pin assignments listed in Table 4.5.

Figure 4.8 Schematic diagram of the clock circuit

CLOCK_27 PIN_D13 27 MHz clock input CLOCK_50 PIN_N2 50 MHz clock input EXT_CLOCK PIN_P26 External (SMA) clock input

Table 4.5 Pin assignments for the clock inputs.

Using the LCD Module

The LCD module features built-in fonts for text display, utilizing commands sent to the HD44780 display controller Comprehensive usage information is accessible in the datasheet available on the manufacturer's website and on the DE2 System CD-ROM Figure 4.9 illustrates the schematic diagram of the LCD module's connections to the Cyclone II FPGA, while Table 4.6 lists the corresponding pin assignments.

Figure 4.9 Schematic diagram of the LCD module

LCD_DATA[0] PIN_J1 LCD Data[0]

LCD_DATA[2] PIN_H1 LCD Data[2]

The LCD_RW pin (K4) determines the read/write mode, where 0 indicates a write operation and 1 signifies a read operation The LCD_EN pin (K3) is responsible for enabling the LCD, while the LCD_RS pin (K1) selects between command and data, with 0 for command and 1 for data Lastly, the LCD_ON pin (L4) controls the power state of the LCD, allowing it to be turned on or off.

LCD_BLON PIN_K2 LCD Back Light ON/OFF

Table 4.6 Pin assignments for the LCD module

Using the Expansion Header

The DE2 Board features two 40-pin expansion headers that interface with 36 pins on the Cyclone II FPGA, supplying DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins Each pin is equipped with protective circuitry, including diodes and a resistor, safeguarding against high and low voltage levels While Figure 4.10 illustrates the protection for only four pins on each header, this circuitry is present for all 72 data pins Detailed pin assignments can be found in Table 4.7.

Figure 4.10 Schematic diagram of the expansion headers

Table 4.7 Pin assignments for the expansion headers.

Using VGA

The DE2 board features a 16-pin D-SUB connector for VGA output, utilizing synchronization signals directly from the Cyclone II FPGA It employs the Analog Devices ADV7123 triple 10-bit high-speed video DAC to generate analog data signals in red, green, and blue Capable of supporting resolutions up to 1600 x 1200 pixels at 100 MHz, the associated schematic is illustrated in Figure 4.11.

The VGA synchronization timing specifications for RGB data are detailed on various educational websites, often found by searching for "VGA signal timing." As illustrated in Figure 4.12, an active-low pulse of specific duration indicates the end of one row and the beginning of the next on a VGA monitor After the horizontal synchronization (hsync) pulse, the RGB data inputs must be turned off for a period known as the back porch, followed by the display interval where each pixel is driven sequentially Prior to the next hsync pulse, the RGB signals must again be off during the front porch period The vertical synchronization (vsync) timing mirrors the horizontal timing, with the vsync pulse marking the transition between frames, encompassing the set of rows in each frame Figures 4.13 and 4.14 provide detailed timing durations for different resolutions, highlighting the time periods for both horizontal and vertical synchronization.

For comprehensive guidance on utilizing the ADV7123 video DAC, refer to the manufacturer's datasheet available on their website and in the Datasheet folder on the DE2 System CD-ROM Pin assignments between the Cyclone II FPGA and the ADV7123 are detailed in Table 4.8, while coding examples for driving a VGA display can be found in Sections 5.2 and 5.3.

Figure 4.12 VGA horizontal timing specification

VGA mode Horizontal Timing Spec

Configuration Resolution(HxV) a(us) b(us) c(us) d(us) Pixel clock(Mhz) VGA(60Hz) 640x480 3.8 1.9 25.4 0.6 25 (640/c) VGA(85Hz) 640x480 1.6 2.2 17.8 1.6 36 (640/c) SVGA(60Hz) 800x600 3.2 2.2 20 1 40 (800/c) SVGA(75Hz) 800x600 1.6 3.2 16.2 0.3 49 (800/c) SVGA(85Hz) 800x600 1.1 2.7 14.2 0.6 56 (800/c) XGA(60Hz) 1024x768 2.1 2.5 15.8 0.4 65 (1024/c) XGA(70Hz) 1024x768 1.8 1.9 13.7 0.3 75 (1024/c) XGA(85Hz) 1024x768 1.0 2.2 10.8 0.5 95 (1024/c) 1280x1024(60Hz) 1280x1024 1.0 2.3 11.9 0.4 108 (1280/c)

Figure 4.13 VGA horizontal timing specification

VGA mode Vertical Timing Spec

Configuration Resolution (HxV) a(lines) b(lines) c(lines) d(lines) VGA(60Hz) 640x480 2 33 480 10 VGA(85Hz) 640x480 3 25 480 1 SVGA(60Hz) 800x600 4 23 600 1 SVGA(75Hz) 800x600 3 21 600 1 SVGA(85Hz) 800x600 3 27 600 1 XGA(60Hz) 1024x768 6 29 768 3 XGA(70Hz) 1024x768 6 29 768 3 XGA(85Hz) 1024x768 3 36 768 1 1280x1024(60Hz) 1280x1024 3 38 1024 1

Figure 4.14 VGA vertical timing specification

VGA_CLK PIN_B8 VGA Clock VGA_BLANK PIN_D6 VGA BLANK

VGA_HS PIN_A7 VGA H_SYNC

VGA_VS PIN_D8 VGA V_SYNC VGA_SYNC PIN_B7 VGA SYNC

Using the 24-bit Audio CODEC

The DE2 board features the Wolfson WM8731 audio CODEC, delivering superior 24-bit audio quality This versatile chip accommodates microphone-in, line-in, and line-out ports, with a customizable sample rate ranging from 8 kHz to 96 kHz Control of the WM8731 is facilitated through a serial I2C bus interface connected to the Cyclone II FPGA pins For a visual representation of the audio circuitry, refer to Figure 4.15, while the FPGA pin assignments are detailed in Table 4.9 Comprehensive usage information for the WM8731 codec is available in its datasheet, accessible on the manufacturer's website and within the Datasheet folder on the DE2 System CD-ROM.

The AUD_ADCLRCK (PIN_C5) and AUD_DACLRCK (PIN_C6) are responsible for the left-right clock signals of the Audio CODEC's ADC and DAC, respectively The AUD_ADCDAT (PIN_B5) and AUD_DACDAT (PIN_A4) handle the data output for the ADC and DAC of the Audio CODEC Additionally, the AUD_XCK (PIN_A5) provides the chip clock for the Audio CODEC, while the AUD_BCLK (PIN_B4) manages the bit-stream clock For I2C communication, the I2C_SCLK (PIN_A6) functions as the data clock, and the I2C_SDAT (PIN_B6) carries the I2C data.

Table 4.9 Audio CODEC pin assignments

RS-232 Serial Port

The DE2 board features the MAX232 transceiver chip along with a 9-pin D-SUB connector for RS-232 communications For comprehensive guidance on utilizing the transceiver, please consult the datasheet available on the manufacturer's website and in the Datasheet folder on the DE2.

System CD-ROM Figure 4.16 shows the related schematics, and Table 4.10 lists the Cyclone II

Figure 4.16 MAX232 (RS-232) chip schematic

UART_RXD PIN_C25 UART Receiver UART_TXD PIN_B25 UART Transmitter

PS/2 Serial Port

The DE2 board features a standard PS/2 interface, allowing for the connection of a PS/2 keyboard or mouse For detailed instructions on utilizing a PS/2 mouse or keyboard, users can refer to various educational websites Additionally, the pin assignments for this interface are outlined in Table 4.11, and the schematic of the PS/2 circuit is illustrated in Figure 4.17.

PS2_CLK PIN_D26 PS/2 Clock PS2_DAT PIN_C24 PS/2 Data

Fast Ethernet Network Controller

The DE2 board features Ethernet connectivity through the Davicom DM9000A Fast Ethernet controller, which includes a general processor interface, 16 Kbytes of SRAM, a media access control (MAC) unit, and a 10/100M PHY transceiver For a detailed schematic of the Fast Ethernet interface and its pin assignments, refer to Figure 4.18 and Table 4.12, respectively For comprehensive usage guidelines, consult the DM9000A datasheet and application note available on the manufacturer's website and in the Datasheet folder on the DE2 System CD-ROM.

ENET_DATA[0] PIN_D17 DM9000A DATA[0]

ENET_DATA[1] PIN_C17 DM9000A DATA[1]

ENET_DATA[2] PIN_B18 DM9000A DATA[2]

ENET_DATA[3] PIN_A18 DM9000A DATA[3]

ENET_DATA[10] PIN_C19 DM9000A DATA[10]

ENET_DATA[14] PIN_E18 DM9000A DATA[14]

ENET_CLK PIN_B24 DM9000A Clock 25 MHz ENET_CMD PIN_A21 DM9000A Command/Data Select, 0 = Command, 1 = Data ENET_CS_N PIN_A23 DM9000A Chip Select

ENET_INT PIN_B21 DM9000A Interrupt ENET_RD_N PIN_A22 DM9000A Read ENET_WR_N PIN_B22 DM9000A Write ENET_RST_N PIN_B23 DM9000A Reset

Table 4.12 Fast Ethernet pin assignments.

TV Decoder

The DE2 board features the Analog Devices ADV7181 TV decoder chip, an integrated video decoder that automatically detects and converts standard analog baseband television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with 16-bit/8-bit CCIR601/CCIR656 This versatile decoder is compatible with various video devices, such as DVD players, tape-based sources, broadcast sources, and security/surveillance cameras.

The TV decoder registers can be programmed via a serial I2C bus connected to the Cyclone II FPGA, as shown in Figure 4.19, with pin assignments detailed in Table 4.13 For comprehensive information on the ADV7181, refer to the manufacturer's website and the Datasheet folder on the DE2 System CD-ROM.

TD_DATA[0] PIN_J9 TV Decoder Data[0]

TD_DATA[1] PIN_E8 TV Decoder Data[1]

TD_DATA[2] PIN_H8 TV Decoder Data[2]

TD_DATA[3] PIN_H10 TV Decoder Data[3]

TD_DATA[4] PIN_G9 TV Decoder Data[4]

TD_DATA[5] PIN_F9 TV Decoder Data[5]

TD_DATA[6] PIN_D7 TV Decoder Data[6]

TD_DATA[7] PIN_C7 TV Decoder Data[7]

TD_HS PIN_D5 TV Decoder H_SYNC TD_VS PIN_K9 TV Decoder V_SYNC

TD_CLK27 PIN_C16 TV Decoder Clock Input

TD_RESET PIN_C4 TV Decoder Reset I2C_SCLK PIN_A6 I2C Data I2C_SDAT PIN_B6 I2C Clock

Table 4.13 TV Decoder pin assignments

Implementing a TV Encoder

The DE2 board lacks a TV encoder chip, but it can utilize the ADV7123, a 10-bit high-speed triple ADC, to create a professional-quality TV encoder, with the digital processing handled by the Cyclone II FPGA This setup is illustrated in Figure 4.20, which presents a block diagram of the TV encoder.

Figure 4.20 A TV Encoder that uses the Cyclone II FPGA and the ADV7123.

Using USB Host and Device

The DE2 board features USB host and device interfaces powered by the Philips ISP1362 single-chip USB controller, adhering to the Universal Serial Bus Specification Rev 2.0 This setup enables data transfer rates of up to 12 Mbit/s for full-speed and 1.5 Mbit/s for low-speed connections For further details, refer to the schematic diagram of the USB circuitry in Figure 4.21 and the pin assignments provided in Table 4.14.

For comprehensive guidance on utilizing the ISP1362 device, refer to its datasheet and programming guide, available on the manufacturer's website and the DE2 System CD-ROM The most complex aspect of a USB application lies in designing the necessary software driver Sections 5.3 and 5.4 offer two complete examples of USB drivers for both host and device applications, showcasing software drivers specifically for the Nios II processor.

Figure 4.21 USB (ISP1362) host and device schematic

OTG_ADDR[0] PIN_K7 ISP1362 Address[0]

OTG_ADDR[1] PIN_F2 ISP1362 Address[1]

OTG_DATA[0] PIN_F4 ISP1362 Data[0]

OTG_DATA[1] PIN_D2 ISP1362 Data[1]

OTG_DATA[2] PIN_D1 ISP1362 Data[2]

OTG_DATA[3] PIN_F7 ISP1362 Data[3]

OTG_DATA[4] PIN_J5 ISP1362 Data[4]

OTG_DATA[7] PIN_H6 ISP1362 Data[7]

OTG_DATA[8] PIN_E2 ISP1362 Data[8]

OTG_DATA[9] PIN_E1 ISP1362 Data[9]

OTG_DATA[10] PIN_K6 ISP1362 Data[10]

OTG_DATA[12] PIN_G4 ISP1362 Data[12]

OTG_DATA[13] PIN_G3 ISP1362 Data[13]

OTG_CS_N PIN_F1 ISP1362 Chip Select OTG_RD_N PIN_G2 ISP1362 Read

The ISP1362 USB controller features several important pins for its operation: the OTG_WR_N (PIN_G1) is used for writing, while the OTG_RST_N (PIN_G5) serves as a reset function Interrupts are managed through OTG_INT0 (PIN_B3) and OTG_INT1 (PIN_C3) For DMA operations, OTG_DACK0_N (PIN_C2) and OTG_DACK1_N (PIN_B2) provide DMA acknowledge signals, while OTG_DREQ0 (PIN_F6) and OTG_DREQ1 (PIN_E5) handle DMA requests Additionally, OTG_FSPEED (PIN_F3) controls USB full speed with a value of 0 to enable and Z to disable, and OTG_LSPEED (PIN_G6) manages USB low speed, similarly allowing 0 for enable and Z for disable.

Table 4.14 USB (ISP1362) pin assignments.

Using IrDA

The DE2 board facilitates straightforward wireless communication through the Agilent HSDL-3201 low power infrared transceiver, with a maximum transmission rate of 115.2 Kbit/s, requiring both TX and RX sides to operate at the same rate For a detailed schematic of the IrDA communication link, refer to Figure 4.22 Additional information on sending and receiving data via the IrDA link can be found at http://techtrain.microchip.com/webseminars/documents/IrDA_BW.pdf.

The pin assignment of the associated interface are listed in Table 4.15

IRDA_TXD PIN_AE24 IRDA Transmitter IRDA_RXD PIN_AE25 IRDA Receiver

Using SDRAM/SRAM/Flash

The DE2 board is equipped with 8 Mbytes of SDRAM, 512 Kbytes of SRAM, and 4 Mbytes of Flash memory (1 Mbyte on some boards) Detailed schematics of the memory chips can be found in Figures 4.23, 4.24, and 4.25, while the pin assignments for each device are outlined in Tables 4.16, 4.17, and 4.18 For additional information, the datasheets for the memory chips are available in the Datasheet folder on the DE2 System CD-ROM.

DRAM_ADDR[0] PIN_T6 SDRAM Address[0]

DRAM_ADDR[1] PIN_V4 SDRAM Address[1]

DRAM_ADDR[3] PIN_W2 SDRAM Address[3]

DRAM_ADDR[5] PIN_U6 SDRAM Address[5]

DRAM_ADDR[10] PIN_Y1 SDRAM Address[10]

DRAM_DQ[0] PIN_V6 SDRAM Data[0]

DRAM_DQ[1] PIN_AA2 SDRAM Data[1]

DRAM_DQ[3] PIN_Y3 SDRAM Data[3]

DRAM_DQ[4] PIN_Y4 SDRAM Data[4]

DRAM_DQ[5] PIN_R8 SDRAM Data[5]

DRAM_DQ[6] PIN_T8 SDRAM Data[6]

DRAM_DQ[7] PIN_V7 SDRAM Data[7]

DRAM_DQ[8] PIN_W6 SDRAM Data[8]

DRAM_DQ[9] PIN_AB2 SDRAM Data[9]

DRAM_DQ[10] PIN_AB1 SDRAM Data[10]

DRAM_DQ[13] PIN_AC2 SDRAM Data[13]

DRAM_DQ[14] PIN_AC1 SDRAM Data[14]

DRAM_BA_0 PIN_AE2 SDRAM Bank Address[0]

DRAM_BA_1 PIN_AE3 SDRAM Bank Address[1]

The SDRAM interface includes several critical pins: the DRAM_LDQM pin (AD2) serves as the Low-byte Data Mask, while the DRAM_UDQM pin (Y5) functions as the High-byte Data Mask The DRAM_RAS_N pin (AB4) is responsible for the Row Address Strobe, and the DRAM_CAS_N pin (AB3) acts as the Column Address Strobe Additionally, the DRAM_CKE pin (AA6) enables the clock, and the DRAM_CLK pin (AA7) provides the clock signal For write operations, the DRAM_WE_N pin (AD3) is utilized for Write Enable, and the DRAM_CS_N pin (AC3) is designated for Chip Select.

SRAM_ADDR[0] PIN_AE4 SRAM Address[0]

SRAM_ADDR[1] PIN_AF4 SRAM Address[1]

SRAM_ADDR[2] PIN_AC5 SRAM Address[2]

SRAM_ADDR[4] PIN_AD4 SRAM Address[4]

SRAM_ADDR[6] PIN_AE5 SRAM Address[6]

SRAM_ADDR[7] PIN_AF5 SRAM Address[7]

SRAM_ADDR[10] PIN_V10 SRAM Address[10]

SRAM_ADDR[11] PIN_V9 SRAM Address[11]

SRAM_ADDR[13] PIN_W8 SRAM Address[13]

SRAM_ADDR[14] PIN_W10 SRAM Address[14]

SRAM_ADDR[15] PIN_Y10 SRAM Address[15]

SRAM_ADDR[16] PIN_AB8 SRAM Address[16]

SRAM_DQ[0] PIN_AD8 SRAM Data[0]

SRAM_DQ[1] PIN_AE6 SRAM Data[1]

SRAM_DQ[2] PIN_AF6 SRAM Data[2]

SRAM_DQ[3] PIN_AA9 SRAM Data[3]

SRAM_DQ[5] PIN_AB10 SRAM Data[5]

SRAM_DQ[7] PIN_Y11 SRAM Data[7]

SRAM_DQ[12] PIN_W11 SRAM Data[12]

SRAM_DQ[13] PIN_W12 SRAM Data[13]

SRAM_DQ[14] PIN_AC9 SRAM Data[14]

SRAM_DQ[15] PIN_AC10 SRAM Data[15]

The SRAM_WE_N (PIN_AE10) is the Write Enable signal for SRAM, while the SRAM_OE_N (PIN_AD10) serves as the Output Enable The SRAM_UB_N (PIN_AF9) functions as the High-byte Data Mask, and the SRAM_LB_N (PIN_AE9) acts as the Low-byte Data Mask Additionally, the SRAM_CE_N (PIN_AC11) is responsible for Chip Enable in SRAM operations.

FL_ADDR[0] PIN_AC18 FLASH Address[0]

FL_ADDR[1] PIN_AB18 FLASH Address[1]

FL_ADDR[2] PIN_AE19 FLASH Address[2]

FL_ADDR[3] PIN_AF19 FLASH Address[3]

FL_ADDR[6] PIN_Y16 FLASH Address[6]

FL_ADDR[7] PIN_AA16 FLASH Address[7]

FL_ADDR[8] PIN_AD17 FLASH Address[8]

FL_ADDR[12] PIN_W16 FLASH Address[12]

FL_ADDR[13] PIN_W15 FLASH Address[13]

FL_ADDR[15] PIN_AD16 FLASH Address[15]

FL_ADDR[18] PIN_AB15 FLASH Address[18]

FL_ADDR[19] PIN_AA15 FLASH Address[19]

FL_DQ[0] PIN_AD19 FLASH Data[0]

FL_DQ[1] PIN_AC19 FLASH Data[1]

FL_DQ[2] PIN_AF20 FLASH Data[2]

FL_DQ[3] PIN_AE20 FLASH Data[3]

FL_DQ[4] PIN_AB20 FLASH Data[4]

FL_DQ[5] PIN_AC20 FLASH Data[5]

FL_DQ[6] PIN_AF21 FLASH Data[6]

FL_DQ[7] PIN_AE21 FLASH Data[7]

FL_CE_N PIN_V17 FLASH Chip Enable FL_OE_N PIN_W17 FLASH Output Enable FL_RST_N PIN_AA18 FLASH Reset FL_WE_N PIN_AA17 FLASH Write Enable

Examples of Advanced Demonstrations

DE2 Factory Configuration

The DE2 board comes pre-configured from the factory to showcase its fundamental features Below are the setup instructions and the locations of the necessary files for this demonstration.

Demonstration Setup, File Locations, and Instructions

• Bit stream used: DE2_Default.sof or DE2_Default.pof

To begin using the DE2 board, ensure it is powered on and connected via USB to the USB Blaster port If the default factory configuration is not stored in the EPCS16 device, download the necessary bit stream to the board using either JTAG or AS programming methods.

The 7-segment displays are currently showing a sequence of characters, while the red and green LEDs are flashing, welcoming you to the Altera DE2.

Board is shown on the LCD display

• Optionally connect a VGA display to the VGA D-SUB connector When connected, the VGA display should show a pattern of colors

• Optionally connect a powered speaker to the stereo audio-out jack

To activate the audio features, set toggle switch SW17 to the UP position to produce a 1 kHz humming sound from the audio-out port Conversely, when switch SW17 is in the DOWN position, you can connect a microphone to the microphone-in port to capture voice sounds or use the line-in port to play audio from a compatible sound source.

The Verilog source code for this demonstration is located in the DE2_Default folder, which contains all essential files for the Quartus II project The main Verilog file, DE2_Default.v, serves as a template for future projects by defining ports that align with all user-accessible pins on the Cyclone II FPGA.

TV Box Demonstration

This demonstration showcases the playback of video and audio from a DVD player through the VGA output and audio CODEC on the DE2 board As illustrated in Figure 5.1, the design features two primary components: I2C_AV_Config and TV_to_VGA The TV_to_VGA component includes several key elements, such as the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444 conversion, YCrCb to RGB conversion, and VGA output.

Controller The figure also shows the TV Decoder (ADV7181) and the VGA DAC (ADV7123) chips used

Upon downloading the bit stream into the FPGA, the register values of the TV Decoder chip are configured through the I2C_AV_Config block, which utilizes the I2C protocol for communication After the power-on sequence, the TV Decoder chip experiences a temporary instability, which is monitored by the Lock Detector.

The ITU-R 656 Decoder block efficiently extracts YCrCb 4:2:2 (YUV 4:2:2) video signals from the ITU-R 656 data stream provided by the TV Decoder, while generating a data valid control signal to indicate the valid output period To address the interlaced nature of the video signal, de-interlacing is performed using an SDRAM Frame Buffer and a field selection multiplexer (MUX), which is controlled by the VGA controller.

Internally, the VGA Controller generates data request and odd/even selected signals to the SDRAM

Frame Buffer and filed selection multiplexer(MUX) The YUV422 to YUV444 block converts the selected YCrCb 4:2:2 (YUV 4:2:2) video data to the YCrCb 4:4:4 (YUV 4:4:4) video data format

The YCrCb_to_RGB block transforms YCrCb data into RGB format, while the VGA Controller block produces standard VGA sync signals, VGA_HS and VGA_VS, to facilitate display on a VGA monitor.

Figure 5.1 Block diagram of the TV box demonstration

• Bit stream used: DE2_TV.sof or DE2_TV.pof

To set up your DVD player with the DE2 board, connect the composite video output (yellow plug) of the DVD player to the Video-in RCA jack on the DE2 board Ensure that the DVD player is configured to output in NTSC format, with a refresh rate of 60 Hz and a 4:3 aspect ratio for optimal performance.

• Connect the VGA output of the DE2 board to a VGA monitor (both LCD and CRT type of monitors should work)

To set up audio output from a DVD player to the DE2 board, connect the DVD player's audio output to the line-in port of the DE2 board, and then attach a speaker to the line-out port If the DVD player's audio jacks are RCA type, use an adaptor to convert them to the mini-stereo plug compatible with the DE2 board, which is also commonly used with most computers.

• Load the bit stream into FPGA Press KEY0 on the DE2 board to reset the circuit

Figure 5.2 illustrates the setup for this demonstration

Figure 5.2 The setup for the TV box demonstration.

USB Paintbrush

The DE2 board offers a comprehensive USB solution for multimedia products, supporting both host and device applications In this demonstration, we showcase a Paintbrush application that utilizes a USB mouse as the input device.

This demonstration showcases the implementation of a USB mouse movement detector using the Philips ISP1362 chip and the Nios II processor It features a video frame buffer with a VGA controller for real-time image storage and display The circuit block diagram, illustrated in Figure 5.3, enables users to draw lines on the VGA display screen with the USB mouse Additionally, the VGA Controller is integrated into the Altera Avalon bus, allowing control by the Nios II processor.

Upon initiating the program on the Nios II processor, it detects the connected USB mouse on the DE2 board As the mouse is moved, the Nios II processor tracks its movements and stores the data in frame buffer memory, while the VGA Controller overlays the visual output.

58 data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display

Figure 5.3 Block diagram of the USB paintbrush demonstration

Project directory: DE2_NIOS_HOST_MOUSE_VGA

Bit stream used: DE2_NIOS_HOST_MOUSE_VGA.sof

Nios II Workspace: DE2_NIOS_HOST_MOUSE_VGA

• Connect a USB Mouse to the USB Host Connector (type A) of the DE2 board

• Load the bit stream into FPGA

• Run the Nios II and choose DE2_NIOS_HOST_MOUSE_VGA as the workspace Click on the Compile and Run button

• You should now be able to observe a blue background with an Altera logo on the VGA display

• Move the USB mouse and observe the corresponding movements of the cursor on the screen

• Left-click mouse to draw white dots/lines and right-click the mouse to draw blue dots/lines on the screen

Figure 5.4 The setup for the USB paintbrush demonstration.

USB Device

Most USB applications function as USB devices instead of USB hosts This demonstration illustrates how the DE2 board can serve as a USB device connected to a host computer As shown in the block diagram (Figure 5.5), the Nios II processor facilitates communication with the host computer through the host port on the DE2 board's Philips ISP1362 device.

To initialize the Philips ISP1362 chip on the DE2 board, connect it to a USB port on the host computer and execute the necessary software program on the Nios II processor Upon successful execution, the host computer will recognize the new device in its USB device list and prompt for the appropriate driver, identifying the device as a Philips PDIUSBD12 SMART.

After installing the driver on the host computer, the next step is to execute the ISP1362DcUsb.exe software, which facilitates communication with the DE2 evaluation board.

In the ISP1362DcUsb program, clicking the Add button triggers the host computer to send a specific USB packet to the DE2 board, which is received by the Nios II processor, resulting in an increment of a hardware counter This updated counter value is displayed on one of the board's 7-segment displays and on the green LEDs Conversely, clicking the Clear button sends a different USB packet to the board, prompting the Nios II processor to reset the hardware counter to zero.

Figure 5.5 Block diagram of the USB device demonstration

• Project directory: DE2_NIOS_DEVICE_LED\HW

• Bit stream used: DE2_NIOS_DEVICE_LED.sof

• Nios II Workspace: DE2_NIOS_DEVICE_LED\HW

• Borland BC++ Software Driver: DE2_NIOS_DEVICE_LED\SW

• Run Nios II IDE with HW as the workspace Click on Compile and Run

• Connect the USB Device connector of the DE2 board to the host computer using a USB cable (type A → B) A new USB hardware device will be detected

• Specify the location of the driver as DE2_NIOS_DEVICE_LED\D12test.inf (Philips PDIUSBD12 SMART Evaluation Board) Ignore any warning messages produced during installation

• The host computer should report that a Philips PDIUSBD12 SMART Evaluation Board is now installed

To begin the demonstration, launch the software DE2_NIOS_DEVICE_LED\SW\ISP1362DcUsb.exe on your host computer Experiment with the application by utilizing the ADD and Clear buttons, as shown in Figure 5.6.

Figure 5.6 The setup for the USB paintbrush demonstration.

A Karaoke Machine

This article outlines the creation of a Karaoke Machine application using the DE2 board, utilizing its microphone-in, line-in, and line-out ports The Wolfson WM8731 audio CODEC operates in master mode, automatically generating the AD/DA serial bit clock (BCK) and left/right channel clock (LRCK) Configuration of the audio CODEC is achieved through the I2C interface, allowing for the adjustment of sample rate and gain The audio input from the line-in port is mixed with the microphone input, and the combined output is sent to the line-out port for playback.

In this demonstration, the sample rate is configured to 48 kHz By pressing the pushbutton KEY0, users can adjust the gain of the audio CODEC through the I2C bus, allowing them to cycle through one of the ten predefined volume levels offered by the device.

Figure 5.7 Block diagram of the Karaoke Machine demonstration

• Bit stream used: DE2_i2sound.sof or DE2_i2sound.pof

• Connect a microphone to the microphone-in port (pink color) on the DE2 board

• Connect the audio output of a music-player, such as an MP3 player or computer, to the line-in port (blue color) on the DE2 board

• Connect a headset/speaker to the line-out port (green color) on the DE2 board

• Load the bit stream into the FPGA

• You should be able to hear a mixture of the microphone sound and the sound from the music player

• Press KEY0 to adjust the volume; it cycles between volume levels 0 to 9

Figure 5.8 The setup for the Karaoke Machine.

Ethernet Packet Sending/Receiving

This demonstration illustrates the process of sending and receiving Ethernet packets using the Fast Ethernet controller on the DE2 board Utilizing the Nios II processor and the DM9000A Ethernet PHY/MAC Controller, users can set up a loop-back connection on a single board or connect two DE2 boards for communication.

The Nios II processor transmits 64-byte packets to the DM9000A every 0.5 seconds Upon receipt, the DM9000A adds a four-byte checksum to each packet before forwarding it to the Ethernet port.

The DM9000A monitors incoming packets to verify if the destination MAC address matches that of the DE2 board If the packet's MAC address is identical or if it is a broadcast packet, the DM9000A accepts the packet and triggers an interrupt to the Nios II processor, which subsequently displays the packet contents.

Figure 5.9 Packet sending and receiving using the Nios II processor

• Bit stream used: DE2_NET.sof

• Nios II Workspace: DE2_NET

• Plug a CAT5 loop-back cable into the Ethernet connector of DE2

• Run the Nios II IDE under the workspace DE2_NET

• Click on the Compile and Run button

• You should now be able to observe the contents of the packets received (64-byte packets sent, 68-byte packets received because of the extra checksum bytes)

Figure 5.10 The setup for the Ethernet demonstration.

SD Card Music Player

Many commercial media/audio players use a large external storage device, such as an SD card or

The CF card serves as a storage solution for music and video files, often integrated into players that feature high-quality DAC devices to ensure superior audio quality The DE2 board offers the essential hardware and software required for optimal performance in these multimedia applications.

SD card access and professional audio performance so that it is possible to design advanced multimedia products using the DE2 board

This article demonstrates the implementation of an SD Card Music Player on the DE2 board, utilizing the board's CD-quality audio DAC circuits to play music files stored on an SD card The project employs the Nios II processor to efficiently read and process the music data.

SD Card and use the Wolfson WM8731 audio CODEC to play the music

The audio CODEC operates in slave mode, requiring external circuitry to supply the ADC/DAC serial bit clock (BCK) and left/right channel clock (LRCK) To facilitate clock generation and data flow control, an Audio DAC Controller is utilized, as illustrated in Figure 5.11 This controller is seamlessly integrated into the Avalon bus architecture, enabling the Nios II processor to effectively manage the application.

The Nios II processor monitors the FIFO memory of the Audio DAC Controller during operation, ensuring it does not become full When the FIFO has available space, the processor reads a 512-byte sector and transmits the data to the FIFO through the Avalon bus Operating at a 48 kHz sample rate, the Audio DAC Controller delivers data and clock signals to the audio CODEC Additionally, the design incorporates a mixing feature that blends microphone input with line input to create Karaoke-style effects.

Figure 5.11 Block diagram of the SD music player demonstration

• Project directory: DE2_SD_Card_Audio

• Bit stream used: DE2_SD_Card_Audio.sof

• Nios II Workspace: DE2_SD_Card_Audio

• Format your SD card into FAT16 format

• To play a music file with this demonstration, the file must use the 48KHz sample rate and

16-bit sample resolution WAV format Copy one or more such WAV files onto the

When using a FAT16-formatted SD card, it is essential to note that any WAV file copied onto the card must be removed by reformatting the entire SD card, due to software limitations in this demonstration.

• Run the Nios II IDE under the workspace DE2_SD_Card_Audio

• Connect a headset or speaker to the DE2 board and you should be able to hear the music played from the SD Card

Figure 5.12 The setup for the SD music player demonstration.

Music Synthesizer Demonstration

This demonstration shows how to implement a Multi-tone Electronic Keyboard using DE2 board with a PS/2 Keyboard and a speaker

The PS/2 Keyboard functions as a piano keyboard for input, while the Cyclone II FPGA on the DE2 board acts as the Music Synthesizer SOC, generating music and tones Additionally, the VGA connected to the DE2 board displays the keys pressed during music playback.

The block diagram of the Music Synthesizer design, as illustrated in Figure 5.13, comprises four key components: the DEMO_SOUND block, which stores a demo sound for playback; the PS2_KEYBOARD, responsible for processing user input from a PS/2 keyboard; the STAFF block, which visually represents the keyboard layout on a VGA monitor when keys are pressed; and the TONE_GENERATOR, which serves as the essential core of the music synthesizer system on a chip (SoC).

User can switch the music source either from PS2_KEYBOAD or the DEMO_SOUND block using SW9 To repeat the demo sound, users can press KEY1

The TONE_GENERATOR has two tones: (1) String (2) Brass, which can be controlled by SW0

The audio codec used on the DE2 board has two channels, which can be turned ON/OFF using SW1 and SW2

Figure 5.13 Block diagram of the Music Synthesizer design

• Bit stream used: DE2_Synthesizer.sof or DE2_Synthesizer.pof

• Connect a PS/2 Keyboard to the DE2 board

• Connect the Lineout of the DE2 board to a speaker

• Make sure all the switches (SW[9:0]) are set to 0 (Down Position)

• Press KEY1 on the DE2 board to start the music demo

• Press KEY0 on the DE2 board to reset the circuit

Table 5.1 and 5.2 illustrate the usage of the switches, pushbuttons (KEYs), PS/2 Keyboard

KEY[0] Reset Circuit KEY[1] Repeat the Demo Music SW[0] OFF: BRASS, ON: STRING SW[9] OFF: DEMO, ON: PS2 KEYBOARD SW[1] Channel-1 ON / OFF

Table 5.1 Usage of the switches, pushbuttons (KEYs)

Table 5.2 Usage of the PS/2 Keyboard’s keys.

Tiêu đề	Altera De2 Board De2 Development And Education Board User Manual
Trường học	Altera Corporation
Chuyên ngành	Engineering
Thể loại	User manual
Năm xuất bản	2006
Thành phố	San Jose

Định dạng
Số trang	73
Dung lượng	3,22 MB