Research Problem S t a t e m e n t
Research M o tiv a tio n
The complexity of a design cycle governs the strategy undertaken by an electronic system
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The evolution of electronic design technologies has been marked by a shift towards more abstract design practices as system complexity increases Figure 1-1 illustrates this progression, indicating that higher levels of abstraction in design tools have emerged in response to growing system intricacies [NEW91] In the 1970s, the design process was predominantly manual, encompassing everything from system-level descriptions to the fabrication of Printed Circuit Boards (PCBs) However, by the early 1980s, the introduction of Computer Aided Design (CAD) tools began to facilitate physical synthesis, reducing the reliance on manual processes.
Physical synthesis, also known as technology mapping, involves converting behavioral descriptions into Boolean expressions and resynthesizing them with a new library A key development in this area is silicon compilation, which emerged in the late 1980s alongside the rise of Application Specific Integrated Circuits (ASICs), significantly enhancing the automation of the electronics design process During this time, logic synthesis became a viable alternative to manual design, streamlining tasks related to verification, testing, and library management This process translates Boolean expressions into a netlist of components derived from libraries of logic gates such as NAND, NOR, and XOR, thereby addressing the complexities of electronic design.
In recent years, behavioral synthesis, also known as register-transfer (RT) synthesis, has gained significant traction in CAD systems This process begins with a defined set of states and corresponding register-transfers for each state, where each state is akin to a clock cycle RT synthesis produces a structure in two main components: a data path focused on data processing and a control unit that manages control signal scheduling Application Specific Integrated Module (ASIM) components, particularly Field Programmable Gate Arrays (FPGAs), rely heavily on this synthesis method to manage design complexity The design space is effectively represented in the Y diagram, which will be explored in greater detail in Chapter 3.
Since the 1970s, the evolution of electronics design technologies has established the behavioral level as the highest and most widely accepted level of abstraction in design automation, serving as a fundamental entry point for designers.
The microelectronics industry utilizes the RT level as the highest abstraction for initiating design processes, a standard commonly provided by CAD vendors like Mentor Graphics™ and Viewlogic™.
Research in High Level Synthesis (HLS) emphasizes converting behavioral descriptions into register-transfer (RT) level representations HLS involves transforming these descriptions into interconnected storage and functional units Common algorithms employed in HLS include partitioning, scheduling, and allocation.
Note th a t this observation is consistent with a notion of research preceding the availability of commercial tools.
Another aspect of design is the complexity of tools used to facilitate the design flow
On one hand, tools alleviate certain steps such as the interpretation of a symbol as its
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In the design of Multi-Chip Modules (MCM), it is essential to consider various aspects, each often requiring a different CAD tool This necessitates the use of a suite of tools rather than relying on a single complex application For instance, within the Mentor Graphics™ design environment, four primary families of tools are utilized to effectively manage the placement and routing processes of components, ensuring a coherent and efficient design workflow.
• Capture of the system description using VHSIC Hardware Description Language (VHDL) (a text editor and the package sys_1076™ to compile VHDL design files):
• Synthesis of the VHDL code into a hierarchical structure with the top level containing symbols of dies which are mounted on the substrate of an MCM device (Autologic™ ):
• Design of each die using a Very Large Scale Integration (VLSI) method (IC Station™ ): and finally
• Preparation of the MCM device for fabrication (MCM Station™ ).
The design task involves a total of 11 tools, as shown in Fig 1-3 This process necessitates advanced training that prioritizes understanding the functionalities of these tools over the exploration of new design techniques and technologies.
The design process must begin at the highest level of abstraction to align with the evolving CAD methodologies in response to the rapidly changing electronic design landscape, characterized by ongoing miniaturization and the pursuit of system-on-chip solutions This approach is essential to manage and potentially reduce the complexity inherent in new design processes.
“In order to move upward efficiently, we need to build other languages on top of
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SYNTHESIS procedure m an u ally m anually
IC FABRICATION (Make a die for MCM) CMOSN Fadtty
INVOKE ICStalion AND GENERATE LAYOUT FILE ICStalion
INVOKE ICStalion AND GENERATE LAYOUT FILE ICStalion
WRITE RTL-LEVEL VHDL DESCRIPTION Design Architect VHDL Editor
IC LAYOUT AND FABRICATION (make a die for MCM) CMOSN Fsdity
INVOKE ENWrile AND DIRECT IT
TO WRITE AN ED IF NETLIST Design Manager and ENWrile
COMPILE CHVL DESCRIPTION AND SIMULATE THE FILE System-1076 Compiler in the design Architect and Quicks'm II
CREATE GATE-LEVEL SCHEMATIC AND SIMULATE IT
Schematic capture in Design Architect Component Library and QuickSim H
SYNTHESIZE THE VHDL DESCRIPTION INTO A GATE-LEVEL DESCRIPTION AND SIMULATE TT
Design Architect, Antologic and _ QuickSim II _
SETTING DESTINATION TECHNOLOGY AND OPTIMIZE THE GATE-LEVEL DESCRIPTION AND SIMULATE IT Vendor Library, Design Architect, Antologic a n d Qnkksim H
INVOKE MCM5tatk>n AND GENERATE A MCM-D LAYOUT
Figure 1-3: Mentor G raphics™ ’ Design Tasks
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VHDL to represent fam ilia r concepts used by systems designers” , from DUTT et al in “High-level synthesis : introduction to chip and system design” [DGLW92]
H y p o th e s is
To meet the design challenge outline in the previous section, this research activity is envisioned to:
1 Introduce a new design process using a generalized synthesis approach as shown in Fig 1-4 The emphasis in this thesis is on the front-end synthesis, called Very High Level Logic Synthesis (VHLLS);
2 Introduce the next generation of design automation tools as a practical consequence of a generalized synthesis process;
3 Lessen or a t least m a in tain the complexity of microelectronics systems design by starting a design process a t a higher level of abstraction;
4 Incorporate a high-level specification as the entry level in an automated design flow.
The primary objective of this research is represented by item (1), while item (2) addresses the feasibility of the problem This leads us to formulate the hypothesis: if (1) can define (2), or mathematically expressed as (1) =£• (2), then the truth of (1) implying (2) ((1) =>■ (2)) establishes that properties (3) and (4) emerge from the new design methodology Consequently, the hypothesis ((1) =*► (2))) implies the theorem ((3) A (4)).
To define the next generation of design automation tools, a set of essential characteristics, referred to as C, is introduced These characteristics are influenced by the tool's intended level of abstraction and aim to be non-restrictive, ensuring flexibility in design automation applications.
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Physical Domain Physical Do mam
Behavioral Do mam Behavioral Do mam
Structural Domain Structural Do mam
Physical Do mam Physical Do mam
Low Level Synthesis RTL Synthesis
1: Circuit Level 2: Logic Level 3: Architecture or Register Level 4: System Level
(a) Concept Synthesis (b) System Synthesis (c) Register Transfer Synthesis (d) Logic Synthesis
To establish a theoretical design process, a bounded set is utilized to maintain problem tractability, resulting in a finite set of elements, denoted as C These elements enable the classification of design automation tools based on their distinct characteristics For the next generation of CAD tools, a proposed list of characteristics includes several key features, although this list is not exhaustive, and alternative sets of characteristics can be defined.
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Gener alize d L og ic S y n th e si s
Sequentially decomposable activities involve breaking down an action into a series of sub-actions, a practice commonly employed in engineering Designers utilize a one-step reasoning approach, where each performed action alters the system's configuration, allowing for the next action to build upon this new state This iterative process continues, systematically transforming the system A clear analogy for sequential actions can be found in structured programming languages like C.
Concurrent decomposable activities enable actions to be broken down into sub-actions that can be executed simultaneously This approach allows systems to perform multiple tasks independently, enhancing efficiency However, the reliance on shared resources can create performance bottlenecks, similar to challenges faced in parallel programming.
State transitions refer to a system characterized by a collection of states, with a transition function that facilitates changes between these states Each state represents a specific configuration of the system, while transitions serve as the means to shift from one predefined configuration to another In engineering, the prevalent mechanisms for managing state transitions include Moore and Mealy Finite State Machines (FSM).
• Immediate Mode Change: at any instant and any system status, a system has the ability to apply an operational mode change instantly In most systems, some external
Action, or activity, refers to a specific mode of behavior within a system It can involve complex or time-consuming computations, or it may be defined recursively as a combination of sub-activities that can occur either sequentially or concurrently.
3In the Moore FSM, the output value is depending only on the state of the FSM
* In the Mealy FSM, the output value depends on the transition and the input values of the FSM
Events require immediate attention, especially when a system receives a reset command that demands instant reaction, even during ongoing computations This characteristic emphasizes the necessity for systems to address exceptional events without delay.
Activity completion is essential in systems that require a current activity to be fully finished before initiating a new one, particularly in sequential processes This mechanism ensures that actions are completed in the correct order, which is vital for designers using description languages like VHDL that combine concurrent and sequential statements without a defined completion mechanism.
Delay specification allows for the definition of time constraints that trigger automatic status changes in a system once the set time elapses This feature eliminates the need for a fixed clock rate, a significant limitation in synchronous systems, as it defers the decision on clock rates until after the system's behavior has been validated For instance, if a designer specifies that a system must change its status after 40 ns, various clock rates—such as 25MHz, 50MHz, or 75MHz—can all accurately measure this interval Consequently, the optimal clock rate depends on the specific requirements of the system, making it impossible to determine the best option prior to the design phase.
Asynchronous activities are actions defined within a system that operate independently of a global clock, responding instead to external changes that are not linked to any timing mechanisms A fitting analogy for these asynchronous activities is interrupts, which highlight their reactive nature.
• Design fo r {Testability, Manufacturability, etc}: specific properties are added to the system to meet requirements for testability, manufacturing, etc When a design is
The design methodology varies based on the application, emphasizing different properties for optimal performance In space applications, the focus is on test and fault tolerance, as any failure during a mission is unacceptable Conversely, in consumer electronics, the priority shifts to design for manufacturing, aiming to reduce costs effectively.
A system can be effectively represented through multiple models, as relying on a single description may not adequately capture its complexity By utilizing various appropriate models tailored to the specific type of system being designed, designers can achieve a more comprehensive and accurate representation, ultimately enhancing the overall system description.
Reusability in system design allows for components to be easily repurposed for different projects, significantly optimizing the design process This characteristic helps reduce time-to-market and eliminates repetitive tasks, enhancing overall efficiency in development.
Research G o a ls
To implement th e hypothesis stated in the previous section, the research goals are for mulated as follows:
1 The characterization of the design space along with a set of properties;
2 The formalization of a concept level in which high-level specifications are embedded:
3 The statem ent and formalization of an automatic process to migrate from the concept level to the system level which is called VHLLS and formally defined in Chapter 3 ;
4 The implementation of VHLLS, ta king high-level specifications and translating them
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15 into a behavioral description a t the system level.
Merits and C o n tr ib u tio n s
A new design process is introduced at the front-end of the generalized synthesis process, paving the way for next-generation design automation tools This process necessitates the characterization and formalization of the design space to establish its requirements A set of characteristics is defined to classify design automation tools, notably including a delay specification that allows for time constraints independent of a clock Consequently, a Concept Level is established as a new abstraction above the system level The synthesis process, known as VHLLS, facilitates a connection between the concept level and the behavioral level, emphasizing time encapsulation Unlike traditional tools that rely on a global clock, this approach considers time as a critical constraint that should be fixed later in the design process to optimize clock rate selection To refine the investigation, specific restrictions are imposed, leading to the definition of new metrics and a feasibility study that broadens the representation of the design space, culminating in the VHLLS framework.
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Thesis O r g a n iz a tio n
Chapter 2 explores the current advancements in the CAD domain for microelectronics, highlighting the sophistication of commercial CAD tools Chapter 3 introduces a new level of abstraction in the design process, adapting the design space accordingly In Chapter 4, relevant research on high-level synthesis and specification description styles is reviewed Chapter 5 delves into the VHLLS process, proposing two implementation approaches Chapter 6 introduces the SPECIAL tool, which allows designers to specify systems, enabling the automatic generation of VHDL descriptions through the VHLLS process Chapter 7 presents three case studies that illustrate the advantages and limitations of this approach The article concludes with insights and recommendations for future research in the VHLLS domain.
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CAD D om ain in M icroelectronics
This chapter outlines the objectives of the research and provides an overview of the "CAD domain" concept, along with an assessment of the current state of commercial CAD tools Additionally, it introduces the principles of VHLLS, integrating these essential components for a comprehensive understanding.
Design Process C h a r a c te riz a tio n
This section explores the concepts of design automation and design methodology, highlighting their significance in understanding the motivations behind this research Designers are increasingly concerned that existing methodologies may soon be outdated due to the rapid increase in system complexity This ongoing instability is a recurring theme in the history of CAD, prompting the emergence of a new approach known as Electronic System Design Automation (ESDA).
In the field of microelectronics system devices have become increasingly complex, reach ing densities of millions of transistors per square centimeter It has become more difficult
To effectively manage complexity in integrated circuit design, systems must be developed at abstract levels where functionalities and trade-offs are more comprehensible Design automation plays a crucial role in optimizing design efforts, enhancing productivity, and maintaining competitiveness among engineers It facilitates rapid prototyping, addresses mechanical and physical constraints, and manages mixed-signal systems This approach has led to the creation of sophisticated tools that automate the entire design process, from initial concept to final implementation.
In the development of design automation methods, the primary objectives are to implement the concepts of first-silicon and first-specification to expedite the time-to-market cycle for new devices The first-silicon concept emphasizes minimizing the reliance on time-consuming and costly prototyping by prioritizing simulation during the validation phase of the design process This simulation incorporates back-annotation to address physical constraints like propagation delay and setting time, while also ensuring automatic adherence to physical design rules Consequently, the use of CAD tools is essential for verifying both the functionality and design rules throughout the chip design cycle The second concept, first-specification, aims to limit design iterations to a single cycle, enhancing efficiency in the design process.
1A prototype is viewed as a first physical realization of a design in order to check its behavior against its specifications
This method imports low-level timing information into the system's descriptive level, aiming to create a more realistic simulation of the design.
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The first-silicon concept emphasizes the necessity for precise modeling during the design process, along with accurate estimation of key product quality metrics, including performance and cost.
Commercial tools have reached a level of maturity that allows them to operate with considerable accuracy, comparable to first-silicon standards Currently, researchers and toolmakers are focused on tackling the challenges associated with the first-specification concept, which has led to the emergence of two competing philosophies in the field.
The top-down methodology, known as "describe and synthesize," involves modeling an entire system through high-level abstraction This approach utilizes a synthesis process to break down the system model into more detailed subsystems and lower abstraction levels that align closely with the target technology In contrast, the bottom-up methodology focuses on building the system from its foundational components.
The "capture and simulate" method is a modeling approach that starts with the lowest modules in a system hierarchy and builds the entire system by combining these modules Each module undergoes simulation to verify its functionality, and as modules are combined, larger modules are formed, creating new levels in the hierarchy until the top system level is reached Currently, tools favor a bottom-up methodology when using schematic descriptions, but with the introduction of Hardware Description Languages (HDLs), the top-down approach has become more effective Leading toolmakers like Mentor Graphics™ and Viewlogic™ often integrate both methodologies in their solutions.
3 HDLs are like programming languages but specialized in the description of microelectronics hardware
In FPGA design, a combination of top-down and bottom-up methodologies is essential The process begins with a VHDL description, which aligns with the top-down approach, while utilizing a library of components necessitates a bottom-up strategy This integration results in a mixed methodology description When the design is technology-independent, the top-down approach is preferred, especially when using high-level specifications.
- form of description o f the evolving deaifn
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The design flow model depicted in Fig 2-1, originally defined in [FRE85] and further detailed in Section 2.4, showcases a top-down methodology that progresses from identifying a need to project completion This model is considered idealistic due to the absence of feedback mechanisms, operating under the assumption that each stage yields the optimal design solution Additionally, Fig 2-1 illustrates the principles of first-specification and first-silicon within this idealistic framework.
Circles often symbolize various aspects of the evolving design process, with some indicating specific stages For instance, the circle marked "Need" highlights the essential requirements that kickstart the design journey, while other circles may represent different phases of development.
“selected scheme” is a form of design description:
• rectangles which indicate a design activity such as analyzing the problem or performing a detailed design;
• arrows which sequence description forms and activities.
The design process begins with identifying the "Need," which involves establishing a clear "statement of the problem." Once consensus is reached, the "conceptual design" phase allows for brainstorming various strategies to address the problem These strategies are then refined into a "selected scheme," taking into account high-level attributes such as interface constraints, size, quality, anticipated cost, and device function This stage is characterized by its open-ended nature, resulting in a collection of potential concepts or schemes for the design.
“scheme” is defined as an outline of m ajor functions in the design A scheme should be
Reproduced with permission of the copyright owner Further reproduction prohibited without permission. beyond the established practices The next stage o f the design process is called either the
The "embodiment of schemes," also known as "preliminary design," marks the initial behavioral model where an initial solution is implemented Once a solution strategy is selected, subsequent stages involve a refining process that continues until the final product is completed at the physical level.
This model, even though it is not feasible, illustrates clearly the top-down, first specifi cation and first silicon concepts.
Commercial Tools
This section explores commercial tools that offer graphical interfaces for system description, primarily using high-level synthesis to target programmable-logic components As the complexity of programmable logic increases, designers are transitioning from traditional schematics to hardware description languages (HDLs), marking a significant shift for the emerging generation of design engineers In practice, these engineers often employ a combination of schematics, Abel-like languages, and various HDLs, typically using HDLs for well-defined functions To facilitate this transition and adapt to a new design methodology, some Electronic Design Automation (EDA) vendors provide graphical-entry tools that assist in converting state machine descriptions into HDL files.
Com pany P ro d u ct(s) T yp es o f en try accepted H D L s gener a te d
A lta Group of Cadence Design System
Block diagrams, state ma chines
Hierarchical block diagrams, state machines, schematics
Antares Antares En vironment Graphical Edi tor
Block diagrams, state ma chines
Escalade DesignBook Block diagrams, state ma chines, waveforms
VHDL, Verilog i-Logix Express StateCharts, activity charts, block diagram
Knowledge Base Silicon flowHDL, block- HDL
Block diagrams, flow diagrams VHDL, Verilog
State transition diagrams, state matrix, dataflow dia grams, schematics
Omniview Alchemist State diagrams, timing dia grams, flowcharts, tru th tables
Better State Pro StateCharts, state machines,
Synopsis COSSAP DSP suite, Design Source
C Table 2.1: Graphical HDL Code-Generation Tool Vendors
Electronic System Design Automation (ESDA) tools are essential for generating VHDL code automatically, as evidenced by the vendors listed in Table 2.1 These tools primarily accept state machine entries and can be characterized by the features outlined in Chapter 1.
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C h a ra c te ris tic s C h e c k m a rk
Sequentially Decomposable Activities Concurrently Decomposable Activities
Immediate Mode Change Activity Completion Delay Specification Asynchronous Activities Design for { Testability, Manufacturing, etc } Multiple Model Representations
Reusability Table 2.2: Advanced High-Level Synthesis Tools Characteristics
EDA vendors, such as Aldec™, are simplifying the transition from schematic to HDL with tools that generate HDLs from graphical inputs Aldec™ promotes its Active State Editor™ tool, which allows for programmable logic design using state machines This tool enables designers to create device-independent designs for Complex Programmable Logic Devices (CPLDs) or Field Programmable Gate Arrays (FPGAs) through graphical entry of bus-based state machines In the Aldec™ environment, users can define combinational and sequential outputs, specify active clock edges, and set default and trap states The Active State Editor™ then converts these specifications into synthesis-ready Abel and VHDL files.
From a designer's perspective, Electronic System Design Automation (ESDA) tools serve as valuable learning resources; however, the code they produce lacks the refinement typically achieved by seasoned HDL designers Additionally, design engineers who are used to working with schematics often feel compelled to modify their designs to address behavioral, timing, and area issues This tendency to manipulate the code, even among those lacking extensive HDL experience, poses significant risks.
Unauthorized reproduction of this content is prohibited Altering the code can lead to a disconnection from the original state-machine description, resulting in errors during HDL simulation that may not correspond to the initial description, thus compromising the integrity of the ESDA input.
Many ESDA tools offer block-diagram functions alongside code-generation capabilities, aiding designers in managing the numerous files produced during the design process For those familiar with schematics, these features serve as valuable learning tools, as top-down design methods involve not only mastering code but also adopting a new perspective on design.
One significant drawback of Electronic System Design Automation (ESDA) tools is their performance limitations compared to hand-written designs, particularly in achieving optimal efficiency at the silicon level This creates a trade-off between time and performance, as automatic processes often cannot match the level of optimization that manual design allows Additionally, EDA vendors typically offer tools tailored for specific architectures, such as FPGA, CPLD, or SRAM, frequently using benchmarks from organizations like the Programmable Electronics Performance Corporation (PREP) to market these specialized tools Consequently, changing the targeted architecture can complicate the migration process, making it less straightforward.
Case Study: RAM C e ll
To illustrate the m ost advanced feature of today’s CADs, we define a RAM cell Its specification4 is thus:
This specification is consistently utilized throughout the thesis to provide a unified illustration of description methods, facilitating their comparison Reproduction of this content is prohibited without the permission of the copyright owner.
Random Access Memory (RAM) operates by using read (RD) and write (WD) commands to determine the necessary actions An address bus identifies unique data locations, while a data bus facilitates data manipulation Typically, RAM remains in a "wait state," monitoring for the condition "CS = T’." Once this condition is met, it decodes whether to read or write based on the combination of RD and WR signals.
In RAM operation, WR = !0! indicates read mode, while RD = 'O' and WR = T' signify write mode, with other conditions representing error states The RAM is expected to return to a wait state upon task completion, ideally within 1 nanosecond.
" NRST = ’O’ ” is true, the RAM has to wait for the condition ”NRST = ’1’
When an inconsistency in control signals occurs, the RAM automatically resets to its initial state after 1 ns Following this reset, a series of control signal events (NRST = 'O', NRST = T') transitions the RAM back into the wait state.
In the Mentor Graphics™ environment, System Architect™ serves as a valuable tool for capturing RAM specifications The process begins with creating a context diagram to specify the Input/Output interface, as illustrated in Fig 2-2 Once the context diagram is established, the next step involves detailing the functionality of the RAM.
In the Architect™ framework, it is essential to distinguish between control functions and data transformations As depicted in the data flow diagram (Fig 2-3), control functions are represented under the "control" node, while data transformations take place within the "storage" node.
The control functions are described using a Moore type state machine as shown in Fig. with permission o f the copyright owner Further reproduction prohibited without permission.
Figure 2-2: Context Diagram for RAM in the the M entor G raphics™ Design Environment
A compromise is necessary for the state machine, as the specification states that the RAM enters a wait state after 1 ns during read or write operations However, this requirement is not realized using the description method outlined in this section; instead, it depends on the settle time of a flip-flop component The data transformation is articulated using VHDL syntax, which effectively describes the data storage function The following VHDL code represents the storage function input for System Architect™, including the complete VHDL description generated by the system.
A rchitect™ can be found in Appendix C):
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•READY en _ read en _ write en err AD
Figure 2-3: D ata Flow Diagram for RAM in the Mentor G raphics™ ’ Design Environment
B E G I N Architecture Description o f the storage activity o f the R A M cell vhd lstorage : P R O C E S S ( sensitive list o f this process sta tem ent
A D 'tra n sa ctio n -transaction is an attribute
D IN 'tr a n sa c tio n , defined in V H D L to notice enjread'transaction, -any change on a signal enjw rite' transaction, enjerr'transaction)
D e fin e a list o f constants : it is a nice way o f program m ing
D e fin e a new type : required in V H D L when a table o f vectors needs to be used
T Y P E typejm em ory IS A R R A Y fO T O nb.words - 1) O F B I T V E C T O R fO T O 3);
D e fin e variables : special m eaning in V H D L — it is used only in a sequential statem ent and during sim ulation, the assignm ent o f a variable is instantaneous w hereas a signal has a delay
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Slate Transition Diagram for control'
D efault A ctions e n _ r e a d < * '0^ en_ w rite