Aside 1. VSI State Space Model
2.2.2 Digital PWM: the Uniformly Sampled Implementation
The basic principles described in Section 2.2.1 apply also to the digital implementation of the PWM modulator. In the more direct implementation, also known as “uniformly sampled PWM,” each analog block is replaced by a digital one. The analog comparator function is replaced by a digital comparator, the carrier generator is replaced by a binary counter, and so forth. We can see the typical hardware organization of a digital PWM, of the type we can find inside several microcontrollers and digital signal processors, either as a dedicated peripheral unit or as a special programmable function of the general purpose timer, in Fig. 2.5.
Clock Binary Counter
Duty-Cycle n bits
n bits Binary Comparator
Timer Interrupt
Match Interrupt
Timer count t
Timer interrupt request t
t
Gate signal
Programmed duty-cycle
TS
FIGURE2.5: Simplified organization of a digital pulse width modulator. The binary comparator triggers an interrupt request for the microprocessor any time the binary counter value is equal to the programmed duty-cycle (match condition). At the beginning of the counting period, the gate signal is set to high and goes low at the match condition occurrence.
The principle of operation is straightforward: the counter is incremented at every clock pulse; any time the binary counter value is equal to the programmed duty-cycle (match condi- tion), the binary comparator triggers an interrupt to the microprocessor and, at the same time, sets the gate signal low. The gate signal is set high at the beginning of each counting (i.e., mod- ulation) period, where another interrupt is typically generated for synchronization purposes.
The counter and comparator have a given number of bits,n, which is often 16, but can be as low as 8, in case a very simple microcontroller is used. Actually, depending on the ratio between the durations of the modulation period and the counter clock period, a lower number of bits,Ne, could be available to represent the duty-cycle. The parameterNeis also important to determine the duty-cycle quantization step, which can have a significant impact on the generation of limit cycles, as we will explain in the following chapters. For now it is enough to say that, with this type of modulator, the number Ne of bits needed to represent the duty-cycle is given by the
THE TEST CASE: A SINGLE-PHASE VOLTAGE SOURCE INVERTER 19
following relation:
Ne =floor
⎡
⎣log10
fclock fS
log102
⎤
⎦+1, (2.4)
where fclock is the modulator clock frequency, fS=1/TS is the desired modulation frequency, and thefloorfunction calculates the integer part of its argument. Typical maximum values for fclock are in the few tens of MHz range, while modulation frequencies can be as high as a few hundreds of kHz. Therefore, when the desired modulation period is short, the number of bits, Ne, given by (2.4) will be much lower than the number bits,n, available in the comparator and counter circuits, unless a very high clock frequency is possible.
Fig. 2.5. allows us to discuss another interesting issue about digital PWM, that is the dynamic response delay of the modulator. In the considered case, it is immediate to see that the modulating signal update is performed only at the beginning of each modulation period.
We can model this mode of operation as asample and holdeffect. We can observe that, if we neglect the digital counter and binary comparator operation assuming infinite resolution, the digital modulator works exactly as an analog one, where the modulating signalm(t) is sampled at the beginning of each modulation period and the sampled value kept constant for the whole period.
It is now evident that, because of the sample and hold effect, the response of the mod- ulator to any disturbance, e.g., to one requiring a step change in the programmed duty- cycle value, can take place only during the modulation period following the one where the disturbance actually takes place. Note that this delay effect amounts to a dramatic differ- ence with respect to the analog modulator implementation, where the response could take place already during thecurrentmodulation period, i.e., with negligible delay. Therefore, even if our signal processing were fully analog, without any calculation or sampling delay, pass- ing from an analog to a digital PWM implementation would imply an increase in the sys- tem response delay. We will see how this simple fact implies a significant reduction of the system’s phase margin with respect to the analog case, which often compels the designer to adopt a more conservative regulator design and to accept a lower closed loop system bandwidth.
Since these issues can be considered fundamental for all the following discussions, from the intuitive considerations reported above, we can now move to a precise small-signal Laplace- domain analysis, which might be very useful for a clear understanding of control limitations and delay effects implied by the uniformly sampled PWM.
An equivalent model of the uniformly sampled PWM process is represented in Fig. 2.6(a).
As can be seen, the schematic diagram adopts the typical continuous time model of a sampled
b)
t c(t), m(t)
cPK
t VMO(t)
c(t) m(t)
ms(t)
TS
c)
t c(t), m(t)
cPK
t VMO(t)
c(t) m(t)
ms(t)
TS
d) a)
t cPK
t VMO(t)
c(t)
m(t) ms(t)
TS
c(t), m(t) m(t)
+ - ms(t)
c(t)
VMO(t) ZOH
TS
FIGURE 2.6: Uniformly sampled PWM with single update mode: (a) general block diagram, (b) trailing-edge modulation, (c) leading-edge modulation, (d) triangular carrier modulation.
data system, where an ideal sampler is followed by a zero-order hold (ZOH). The quantization effect that is associated, in the physical implementation of the modulator of Fig. 2.5., with the digital counter and binary comparator operation, is neglected, being irrelevant from the dynamic response delay standpoint. Accordingly, in the model of Fig. 2.6(a), after the modulating signal m(t) is processed by the ZOH, the PWM waveform is generated by an ideal analog comparator, which compares the ZOH output signalms(t) and the carrier waveformc(t).
Depending onc(t), several different uniformly sampled pulse-width modulators can be obtained. For example, in Fig. 2.6(b) a trailing-edge modulation is depicted, where the update of the modulating signal is performed at the beginning of the modulation period. Note that this is an exactly equivalent representation of the modulator organization of Fig. 2.5. In a small-signal approximation, it is possible to find that the transfer function between the modulating signal m(t) and the output of the comparatorVMO(t) is given by [7]
PWM(s)= VMO(s)
M(s) = e−s DTS
cPK , (2.5)
whereVMO(s) and M(s) represent the Laplace transforms of VMO(t) and m(t), respectively.
Therefore, the uniformly sampled modulator presents a delay whose value is proportional to the steady-state duty-cycleD.
In more general terms, the delay introduced by the PWM modulator represents the time distance between the modulating signalm(t) sampling instant and the instant when the output pulse is completely determined (i.e., whenms(t) intersectsc(t) in Fig. 2.6). The result (2.5)
THE TEST CASE: A SINGLE-PHASE VOLTAGE SOURCE INVERTER 21
has been extended also to other types of modulator organizations (trailing edge, triangular carrier, etc.) [8]. For example, for the leading-edge modulation represented in Fig. 2.6(c), the small-signal modulator transfer function turns out to be
PWM(s)= VMO(s)
M(s) = e−s(1−D)TS
cPK , (2.6)
while, for the triangular carrier modulation, where the sampling of the modulating signal is done in the middle of the switchonperiod (Fig. 2.6(d)), it is
PWM(s)= VMO(s) M(s) = 1
2cPK
e−s(1−D)TS2 +e−s(1+D)TS2
. (2.7)
Finally, the case of the triangular carrier modulator, where the sampling of the modulating signal is done in the middle of the switchoff period, can be simply derived from (2.7) substituting DwithD, beingD=1−D.