8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV SCHEM,MBP 15"MLB ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 08/18/2008 (.csa) D Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 28 29 31 32 33 34 35 37 38 39 41 42 43 45 46 48 49 50 51 52 Date Contents Sync Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration JTAG Scan Chain Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port(MiniXDP) MCP CPU Interface MCP Memory Interface MCP Memory Misc MCP PCIe Interfaces MCP Ethernet & Graphics MCP PCI & LPC MCP SATA & USB MCP HDA & MISC MCP Power & Ground MCP79 A01 Silicon Support MCP Standard Decoupling MCP Graphics Support SB Misc FSB/DDR3/FRAMEBUF Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support Right Clutch Connector ExpressCard Connector Ethernet PHY (RTL8211CL) Ethernet & AirPort Support Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port Power FireWire Ports SATA Connectors External USB Connectors Front Flex Support SMC SMC Support LPC+SPI Debug Connector M98 SMBus Connections N/A (.csa) Page TABLE_TABLEOFCONTENTS_HEAD N/A 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A 07/22/2008 TABLE_TABLEOFCONTENTS_ITEM DDR N/A TABLE_TABLEOFCONTENTS_ITEM N/A (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 10/17/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 10/17/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 10/17/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 01/08/2008 TABLE_TABLEOFCONTENTS_ITEM M99_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 AMASON_M98_MLB 12/17/2007 T18_MLB 07/22/2008 DDR 07/22/2008 DDR 07/22/2008 DDR 06/18/2008 T18_MLB 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 08/14/2008 SENSOR 08/14/2008 SENSOR 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/02/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 06/18/2008 T18_MLB 06/18/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 07/22/2008 DDR TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100 101 102 103 Date Contents (.csa) Sync Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors WELLSPRING WELLSPRING Sudden Motion Sensor (SMS) SPI ROM AUDIO:CODEC AUDIO: LINE IN AUDIO: HEADPHONE AMP AUDIO:SPEAKER AMP AUDIO: JACKS AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.5V DDR3 Supply 1.05V / MCP Core Regulator CPU VTT Power Supply Misc Power Supplies Power Control Power FETs NV G96 PCI-E NV G96 Core/FB Power NV G96 Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G96 GPIO/MIO/Misc G96 GPIOs & Straps NV G96 Video Interfaces GPU (G84M) Core Supply LVDS Display Connector Muxed Graphics Support DisplayPort Connector 1.1V / 1V8 FB Power Supply Graphics MUX (GMUX) LCD BACKLIGHT DRIVER LCD Backlight Support Misc Power Supplies CPU/FSB Constraints Memory Constraints MCP Constraints MCP Constraints Page 08/14/2008 TABLE_TABLEOFCONTENTS_HEAD SENSOR 08/14/2008 TABLE_TABLEOFCONTENTS_ITEM SENSOR 08/14/2008 TABLE_TABLEOFCONTENTS_ITEM SENSOR 10/17/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 06/18/2008 AMASON_M98_MLB 05/12/2008 PWRSQNC 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 12/06/2007 T18_MLB 12/10/2007 M99_MLB 10/17/2007 M87_MLB 01/09/2008 M99_MLB 12/13/2007 M99_MLB 01/08/2008 M99_MLB 12/14/2007 M99_MLB 12/14/2007 M99_MLB 05/12/2008 PWRSQNC 05/12/2008 PWRSQNC 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/09/2008 MUXGFX 07/10/2008 MUXGFX 10/17/2007 M87_MLB 02/25/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 02/01/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 91 92 93 94 95 96 104 105 106 107 108 109 Contents Ethernet Constraints FireWire Constraints SMC Constraints GPU (G96) Constraints Project Specific Constraints PCB Rule Definitions D Date Sync 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/21/2008 MUXGFX 01/22/2008 M99_MLB TABLE_TABLEOFCONTENTS_ITEM C B TABLE_TABLEOFCONTENTS_ITEM www.laptop-schematics.com A DIMENSIONS ARE IN MILLIMETERS APPLE INC METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7546 SCHEM,FIBBO,M98 SCH CRITICAL 820-2330 PCBF,FIBBO,M98 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,MBP 15MLB NONE DRAWING SIZE TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Mon Aug 18 01:48:34 2008 THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7546 SHT 1 A.0.0 OF 96 U1000 U1300 INTEL CPU XDP CONN 2.X OR 3.X GHZ PG 12 PENRYN MAIN MEMORY FSB INTERFACE GPIOs UDIMMs DDR2-800MHZ DDR3-1067/1333MHZ POWER SUPPLY PG 60 J2900 DIMM PG 14 U4900 PG 25,26 TEMP SENSOR PG 41 Misc CLK PG 24 U6100 SYNTH J4510 SATA Conn HD POWER PGSENSE 45 SPI Boot ROM SPI J5650,5600,5610,5611,5660,5720,5730,5750 FAN CONN AND CONTROL PG 52 1.05V/3GHZ PG 48,49 PG 20 PG 38 NVIDIA J4520 SATA Conn ODD 1.05V/3GHZ J4900 SMC LPC PG 19 PG 38 ADC B,0 BSB MCP79 SATA Fan Ser Prt J5100 PG 41 LPC Conn Port80,serial C PG 43 PG 18 U1400 J9000 PWR LVDS CONN CTRL LVDS OUT PG 71 RGB OUT J4720 DP OUT DISPLAY PORT CONN HDMI OUT PG 40 DVI OUT TMDS OUT USB PG 71 J4700 Bluetooth PG 17 J4710 J4710 TRACKPAD/ KEYBOARD IR PG 40 PG 40 J3900,4635,4655 CAMERA EXTERNAL USB Connectors PG 40 PG 39 PG 16 J9400 PCI-E A DC/BATT PG 13 UP TO 20 LANES3 B D J6950 800/1067/1333 MHz PG 19 C FSB 64-Bit (UP TO 12 DEVICES) D www.laptop-schematics.com PG B SMB SMB CONN PG 20 RGMII PCI (UP TO FOUR PORTS) HDA PG 44 DIMM’s PG 17 PG 18 PG 20 U6200 Audio Codec PG 53 U6301 U3700 GB E-NET U6400 Line In Amp 88E1116 PG 54 U6500 HEADPHONE Amp Line Out Amp Speaker Amps PG 56 PG 57 PG 55 System Block Diagram U6600,6605,6610,6620 SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PG 31 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400 U3900 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Mini PCI-E AirPort J6800,6801,6802,6803 E-NET Conn Audio Conns PG 28 SIZE DRAWING NUMBER D PG 33 PG 59 APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A M98 POWER SYSTEM ARCHITECTURE ENABLE PPVIN_G3H_P3V42G3H 3.425V G3HOT D6905 PP3V42_G3H_REG LT3470 U6990 (PAGE 59) PBUSB_VSENSE V 8A FUSE PPVBAT_G3H_CHGR_REG Q5315 PPBUS_G3H V U5705 ENABLES 6A FUSE A VIN VOUT A U5715 CPU VCORE VOUT VIN ISL9504B U7100 IMVP_VR_ON_R VR_ON PPVBAT_G3H_CHGR_R PGOOD (PAGE 61) CHGR_BGATE TPS51117 U7600 (PAG 66) PPVCORE_GPU_REG PGOOD CPUVTTS0_PGOOD GPUVCORE_PGOOD A RSMRST* SMC_CPU_VSENSE V MCP_PS_PWRGD CPU_PWRGD PWROK CPUPWRGD(GPIO49) PPVCORE_CPU_S0 CPUVCORE_IOUT VR_PWRGD_CLKEN_L U1400 (PAGE 14~22) U2850 VR_PWRGOOD_DELAY Q7920 CPU P1V1GPU_EN EN1 VIN VOUT1 P5VS3_EN LIO_S3_EN SLP_S3#(G17) U1400 P1V8FB_ENEN2 SMC VOUT2 PP1V1_S0GPU_REG Q7900 PP5V_S3_FET P5VS3_SS TPS51124 U9500 (PAGE 82) U7859 P60 SMC_PM_G2_EN VIN 5V VOUT1 PP5V_S5_REG (8A MAX CURRENT) 3.3V VOUT2 (R/H) P3V3S5_EN VIN U7400 PP5V_RT_REG VOUT EN/PSV SC417 P5V_RT_EN (PAGE 64) P5V_RT_PGOOD ENL PGOOD PP5V_S3 (L/H) (S5) (PAGE 42) (PAGE 14~22) PP3V3_S5_REG (5.5A MAX CURRENT) TPS51125 PP3V3_S5 PP3V3_S3_FET (PAGE 62) PGOOD1,2VREG3 P3V3S3_SS P5V3V3_S5_PGOOD Q7930 SMC PP3V3_S0GPU_FET PM_WLAN_EN_L WOW_EN PP1V05_S5_MCP ISL8009 V4 U7750 (PAGE 66) Q7910 EN0 U7201 Q3805 B GOSHAWK6P BKLT_EN PM_ENET_EN U9701 PP3V3_S0_FET ENA VOUT (PAGE 84) P1V2ENET_EN ENETAVDD_EN RSMRST_PWRGD Q7970 PPVOUT_S0_LCDBKLT PM_ENET_EN_L Q3800 WOL_EN PM_ENET_EN_L SMC_ADAPTER_EN A P1V8S0_EN RC DELAY RC DELAY PP1V9_ENET_REG DDRVTT_EN VIN P3V3_ENET_FET PP1V2_ENET_REG PM_SLP_S3_L RST* SMC_RESET_L SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93) U4900 (PAGE 42) RST* PP5V_S0 PP3V3_S0 V1 V2 V3 LTC2900 PP1V5_S0_REG V4 U7870 TPS51116 U7300 (PAGE 63) (S0) P1V8S0_PGOOD P1V5S0_PGOOD S0PGOOD_PWROK MCP_CORE MCPDDR_EN RC DELAY P3V3S0_EN (S0) MCPCORES0_EN CPUVTTS0_EN RC DELAY PBUSVSENS_EN (S0) P1V05S0_EN MCPCORES0_EN RC DELAY PM_SLP_S3_DELAY_L EN2 VOUT2 1.1V EN1 VOUT1 MCPCPCORE_S0_REG Power Block Diagram SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY (PAGE 68) (25A MAX CURRENT) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PP5V_RT_REG II NOT TO REPRODUCE OR COPY IT (5A MAX CURRENT) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE ISL6236 VIN U7500 (PAGE 65) (S0) DRAWING NUMBER D APPLE INC REV 051-7546 SCALE SHT NONE B 99ms DLY IMVP_VR_ON IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) PM_PWRBTN_L P17(BTN_OUT) VLDOIN 1.8V S5 VOUT1 PPDDR_S3_REG (12A MAX CURRENT) S3 0.9VVOUT2 PPVTT_S0_DDR_LDO P5VS0_EN P1V05S0_PGOOD P5VRIGHT_PGOOD MCPCORES0_PGOODPM_SLP_S5_L CPUVTTS0_PGOOD PM_SLP_S4_L Q3810 PPVIN_S0_DDRREG_LDO DDRREG_EN SMC_ONOFF_L P3V3GPU_SS VINLTC3407 VOUT1 RUN2 U3850 (PAGE 33) RUN1 VOUT2 P3V3ENET_EN_L P5VRIGHT_EN RC DELAY PWRGD(P12) VIN P3V3S0_SS PM_SLP_S3_L RSMRST_OUT(P15)PM_RSMRST_L ALL_SYS_PWRGD Q3801 PWRGOOD U1000 (PAGE 10,11) RESET* PP1V8_GPU_REG 1.8V(R/H) U4900 C PP5V_S0_FET 1.103V(L/H) SLP_S5#(H17) PWRBTN# VR_PWRGD_CLKENVRMPWRGD P5VS0_SS MCP79 MCP79 CK_PWRGD U2830 PPBUS_G3H P3V3S3_EN D 1.05V PLTRST*PLT_RST_L U5400 Q7055 C PPCPUVTT_S0_REG (6A MAX CURRENT) SMC_BATT_ISENSE J6950 BATT_POS_F VOUT (PAGE 78) ISL6258A U7000 (9 TO 12.6V) EN_PSV GPUVCORE_IOUT(18A MAX CURRENT) PGOOD (PAGE 60) LIO_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER 3S2P A GPU VCORE VOUT VIN ISL6263B U8900 PM_GPUVCORE_EN EN_PSV CHGR_EN (S5) VIN CPUVTTS0_EN SMC_GPU_VSENSE U5498 AC DCIN(16.5V) ADAPTER IN SMC PWRGD RN5VD30A-FSMC_RESET_L U5000 (PAGE 43) D6905 D www.laptop-schematics.com A.0.0 OF 96 A D C C B B www.laptop-schematics.com D Power Block Diagram SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9334 PCBA,2.4GHZ,256SAM_VRAM,M98 M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG 630-9335 PCBA,2.4GHZ,256HYN_VRAM,M98 M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX 630-9336 PCBA,2.5GHZ,512SAM_VRAM,M98 M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG 630-9337 PCBA,2.5GHZ,512QIM_VRAM,M98 M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA 630-9585 PCBA,2.8GHZ,512SAM_VRAM,M98 M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG 630-9586 PCBA,2.8GHZ,512QIM_VRAM,M98 M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D D M98 BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M98_COMMON ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS M98_COMMON1 ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC M98_COMMON2 BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX M98_COMMON3 DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO M98_DEBUG SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN M98_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM www.laptop-schematics.com TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS FB_256_SAMSUNG VRAM4,VRAM_256_SAMSUNG FB_256_HYNIX VRAM4,VRAM_256_HYNIX FB_512_SAMSUNG VRAM4,VRAM_512_SAMSUNG FB_512_QIMONDA VRAM4,VRAM_512_QIMONDA TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Bar Code Labels / EEE #’s C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:0ZA] CRITICAL BOM OPTION EEE_0ZA 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:0ZB] CRITICAL EEE_0ZB 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:0ZC] CRITICAL EEE_0ZC 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:0ZD] CRITICAL EEE_0ZD 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2NH] CRITICAL EEE_2NH 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2NJ] CRITICAL EEE_2NJ C Module Parts B PART NUMBER QTY REFERENCE DES CRITICAL 337S3639 IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA DESCRIPTION U1000 CRITICAL BOM OPTION CPU_2_4GHZ 337S3640 IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA U1000 CRITICAL CPU_2_5GHZ 338S0554 IC,GPU,55nm,NV G96-GS,BGA969,LF U8000 CRITICAL 338S0570 IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP U3700 CRITICAL 338S0523 IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL 338S0600 IC,GMCP,MCP79-B01,35x35MM,BGA1437 U1400 CRITICAL MCP_B01 338S0563 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL SMC_BLANK 341S2289 IC,SMC,DEVELOPMENT,M98 U4900 CRITICAL SMC_PROG 335S0384 IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S2366 IC,EFI ROM,DEVELOPMENT,M98 U6100 CRITICAL BOOTROM_PROG 341S2272 IC,HDCP ROM,NVG96, PIN SOIC,LF,HF U8770 CRITICAL HDCP_YES 341S2384 IR,ENCORE II, CY7C63803-LQXC U4800 CRITICAL 338S0635 IC,GMCP,MCP79-B02,35x35MM,BGA1437 U1400 CRITICAL MCP_B02 341S2383 IC,PSOC +W/USB,56PIN,MLF,M98 U5701 CRITICAL TPAD_PROG 337S3641 IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA U1000 CRITICAL CPU_2_8GHZ 333S0482 IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_SAMSUNG 333S0483 IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX 333S0481 IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG 333S0472 IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_QIMONDA B TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 138S0603 BOM OPTION REF DES COMMENTS: 138S0602 ALL Murata alt to Samsung 353S1681 353S1294 ALL LMV2011,OPAMP GBW 152S0276 152S0683 ALL Maglayers alt to Dale/Vishay 341S2367 341S2366 ALL Macronix alt to SST TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM BOM Configuration TABLE_ALT_ITEM A SYNC_MASTER=N/A TABLE_ALT_ITEM 152S0876 152S0867 ALL NOTICE OF PROPRIETARY PROPERTY TABLE_ALT_ITEM 157S0058 157S0055 ALL SYNC_DATE=N/A Maglayer alt to Delta Delta alt to TDK Magnetics THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_ALT_ITEM 353S2312 353S1466 ALL INTERSIL ALT TO INTERSIL 514-0612 514-0607 ALL FOXLINK XCVR ALT TO FOXCONN 514-0613 514-0608 ALL FOXLINK RCVR ALT TO FOXCONN TABLE_ALT_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_ALT_ITEM 152S0915 152S0796 ALL Maglayers alt to Cyntec IND SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A 1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE) =PP3V3_S0_XDP 13 U1000 CPU From XDP connector JTAG_ALLDEV C0601 0.1UF 20% 10V CERM 402 JTAG_ALLDEV C0602 0.1UF 20% 10V CERM 402 87 13 10 IN 87 13 10 IN 87 13 10 IN 87 13 10 IN XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L D To XDP connector and/or level translator =PP1V05_S0_CPU 62 13 12 11 10 XDP R0603 87 10 XDP_TDO PLACEMENT_NOTE=Place near pin U1000.AB3 XDP_TDO_CONN 5% 1/16W MF-LF 402 13 OUT XDP connector www.laptop-schematics.com D JTAG_ALLDEV R06011 11 10K 5% 1/16W MF-LF 402 From XDP connector or via level translator VCCA VCCB U0600 U1400 MCP NLSV4T244 XDP_TCK 87 13 10 NOSTUFF R0602 87 13 10 87 13 10 5% 1/16W MF-LF 402 XDP_TMS XDP_TRST_L JTAG_LVL_TRANS_EN_L UQFN A1 B1 A2 B2 A3 B3 JTAG_ALLDEV A4 B4 10 MAKE_BASE=TRUE MAKE_BASE=TRUE JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L 13 21 XDP 13 21 23 R0604 13 21 23 13 21 21 JTAG_MCP_TDO R0606 OE* 10K GND PLACEMENT_NOTE=Place near pin U1400.F19 JTAG_MCP_TDO_CONN 13 OUT XDP connector C 5% 1/16W MF-LF 402 C 5% 1/16W MF-LF 402 12 MAKE_BASE=TRUE NOSTUFF U8000 GPU VCC U0601 GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TMS GPU_JTAG_TRST_L 74LVC1G07 A GMUX CPLD Programming Port NC SOT886 GND NC 76 75 =PP3V3_GPU_VDD33 10K PLACEMENT_NOTE=Place close to U8000 GPU_JTAG_TMS 75 5% 1/16W MF-LF 402 75 75 75 75 75 GPU_JTAG_TDO TP_GPU_JTAG_TDO MAKE_BASE=TRUE NC NC Y R0605 CRITICAL PLACEMENT_NOTE=Place close to U0600 J0600 1909782 M-RT-SM =PP3V3_S0_XDP 13 TDO TDI TMS U9200 GMUX B TCK JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TMS B 83 83 83 83 JTAG_GMUX_TDO JTAG Scan Chain A SYNC_MASTER=DDR SYNC_DATE=07/22/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A Functional Test Points ICT Test Points CPU FSB NO_TESTs Fan Connectors NO_TEST FUNC_TEST D TRUE =PP5V_S0_FAN_LT TRUE TRUE FAN_LT_PWM FAN_LT_TACH TRUE TRUE TRUE FAN_RT_PWM FAN_RT_TACH GND 49 TRUE TRUE TRUE FSB_A_L FSB_ADS_L FSB_ADSTB_L TRUE FSB_D_L 10 14 87 TRUE FSB_DINV_L 10 14 87 TRUE TRUE TRUE TRUE TRUE TRUE FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L 10 14 87 10 14 87 10 14 87 TPs per Fan D 49 49 49 49 TPs per Fan 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 www.laptop-schematics.com LVDS Connectors FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE I568 I567 I570 I571 I572 I573 I569 =PP3V3_S0_DDC_LCD PP3V3_SW_LCD BKL_SYNC LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P 76 79 79 Speaker Connectors 79 84 79 80 79 80 FUNC_TEST 79 80 94 I557 79 80 94 I558 TRUE TRUE I574 I566 LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P I559 79 80 94 I560 79 80 94 I561 I575 C I576 TRUE TRUE LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P TRUE TRUE TRUE TRUE LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P I562 79 80 94 I563 79 80 94 I564 I577 I578 I579 I580 79 94 I565 BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT SPKRCONN_S_P_OUT SPKRCONN_S_N_OUT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 58 59 58 59 58 59 57 58 95 57 58 95 57 58 95 57 58 95 79 80 94 TRUE TPs 79 80 94 57 58 95 I757 GND I758 I759 TRUE TRUE I581 I582 LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P 79 80 94 I756 79 80 94 I753 I752 TRUE TRUE I583 I584 TRUE TRUE I585 I586 TRUE TRUE TRUE TRUE TRUE TRUE I587 I588 I590 I589 I592 I591 LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 79 80 94 I754 79 80 94 I755 79 84 I595 79 84 I594 79 84 I596 79 84 I597 79 84 I593 79 84 TRUE TRUE TRUE TRUE TRUE TRUE EXCARD Connector I640 I644 I645 I646 I648 I647 I650 I649 I651 I653 I652 I654 I655 I641 I657 I656 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TPs PP5V_SW_ODD SMC_ODD_DETECT I748 39 I746 39 42 I747 SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P 39 89 I745 39 89 I744 39 89 I743 39 89 I741 GND I742 TPs I740 I739 POWER RAILS FUNC_TEST I643 I750 FUNC_TEST TRUE I642 I749 79 94 I598 B I751 SATA ODD Connectors 79 94 USB2_EXCARD_CONN_N 32 95 USB2_EXCARD_CONN_P 32 95 PCIE_CLK100M_EXCARD_CONN_N 32 95 PCIE_CLK100M_EXCARD_CONN_P 32 95 PCIE_EXCARD_R2D_N 32 89 95 PCIE_EXCARD_R2D_P 32 89 95 PCIE_EXCARD_D2R_P 17 32 89 PCIE_EXCARD_D2R_N 17 32 89 PP3V3_S3_EXCARD_SWITCH 32 PP3V3_S0_EXCARD_SWITCH 32 PP1V5_S0_EXCARD_SWITCH 32 PLT_RESET_SWITCH_L 32 EXCARD_CPPE_L 32 EXCARD_CPUSB_L 32 EXCARD_CLKREQ_CONN_L 32 SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA 13 21 45 90 13 21 45 90 I602 I603 I604 I605 I607 I606 I609 I608 I610 I612 I611 I613 I600 I625 I624 I623 I622 I620 I621 I618 I619 I617 I615 I616 I614 A I627 I626 I639 I638 I637 I636 I709 I760 I761 I762 I765 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PM_SLP_S3_L 21 34 37 42 44 68 81 83 PPBUS_G3H PPBUS_CPU_IMVP_ISNS PP3V42_G3H PP5V_S3 PP5V_S0 PPVCORE_S0_CPU PPVCORE_S0_MCP_REG PPVCORE_S0_MCP PP3V3_S5 PP3V3_S3 PP3V3_S0 PP2V5_S0 PP1V2_S0 I736 43 I737 I735 I734 I733 I731 I732 95 I730 I728 95 I729 I726 I727 I725 I724 I723 I721 I722 I720 I718 I719 I717 I715 I716 I713 I714 8 PP1V8_S0GPU_ISNS PPVCORE_GPU PP1V8_S0GPU_ISNS_R PP3V3_S5_AVREF_SMC PPVOUT_S0_LCDBKLT PPDCIN_G3H PPVTTDDR_S3 PP1V8_GPUIFPX 51 51 51 50 51 50 51 50 51 50 51 50 51 51 50 51 50 51 50 51 50 51 50 51 50 51 50 51 50 51 45 93 45 93 50 51 50 51 KEYBOARD CONN I712 PP1V1_S0GPU_REG IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE B 46 PP1V8_S0 PP1V8R1V5_S3 PP1V8R1V5_S0_FET PPMCPDDR_ISNS PP1V05_S0_REG PP1V2R1V05_S5 PPCPUVTT_S0 PPCPUFSB_ISNS_R PP0V9R0V75_S0_DDRVTT PP1V2R1V05_ENET PP3V3_ENET_PHY PPVP_FW PP1V0_FW PP3V3_S0GPU C 57 58 95 79 94 I711 I710 I763 I764 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD KBDLED_ANODE TPAD_GND_F 43 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 Functional / ICT Test 50 50 SYNC_MASTER=N/A 50 SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY 50 50 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 50 51 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 51 II NOT TO REPRODUCE OR COPY IT 42 43 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 79 84 SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A "G3Hot" (Always-Present) Rails 3.3V-2.5V Rails PPBUS_G3H =PPBUS_G3H 61 46 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE =PPVIN_S5_P5VP3V3 =PPVIN_S5_CPU_IMVP_ISNS 78 46 65 64 67 PPBUS_CPU_IMVP_ISNS =PP3V3_S5_MCPPWRGD =PP3V3_FW_LATEVG =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR 62 PPDCIN_G3H 69 =PP3V3_S3_FET 43 =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_LIDSWITCH =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V3_S5_RTC_D =PP3V42_G3H_BATT =PP3V42_G3H_TPAD =PP3V42_G3H_BMON_ISNS =PP3V42_G3H_CPUCOREISNS =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_VREFMRGN =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_EXCARD =PP3V3_S3_P1V8S0 40 45 41 42 43 52 44 =PP5V_S3_REG =PP3V3_S0_FET 26 50 46 46 =PP5V_S3_SYSLED =PP5V_S3_BTCAMERA =PP5V_S3_WLAN =PP5V_S3_IR 43 31 31 41 =PP5V_S3_DDRREG =PP5V_S3_GPUVCORE =PP5V_S3_RTUSB 79 69 68 69 22 24 =PP1V8R1V5_S0_FET 69 4771 mA 130 mA 500 mA 26 38 34 34 =PP1V8R1V5_S0_MCP_MEM 32 =PP1V0_FW_REG 49 62 66 51 82 44 39 39 PP1V0_FW 67 =PP1V0_FW_FWPHY 36 28 29 "GPU" Rails 47 =PP3V3_S0GPU_FET PP3V3_S0GPU 1034 mA 31 21 27 45 =PP3V3_GPU_VDD33 =PP3V3_GPU_MIO 24 24 67 18 25 68 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 PPVCORE_S0_MCP_REG =PP3V3_GPU_PWRCTL =PP3V3_GPU_VCORELOGIC 78 =PP3V3_GPU_P1V8S0 67 17 PP1V05_S0_MCP_PEX_AVDD 24 MAKE_BASE=TRUE =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 17 82 =PP1V1_S0GPU_REG PP1V1_S0GPU_REG 43 24 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 20 PP1V05_S0_MCP_SATA_AVDD =PP1V05_S0_MCP_SATA_AVDD0 20 =PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD =PP1V1_GPU_PEX_PLLXVDD =PP1V1_GPU_PLLVDD =PP1V1_GPU_H_PLLVDD =PP1V1_GPU_VID_PLLVDD =PP1V1_GPU_FBPLLAVDD =PP1V1_GPU_IFPCD_IOVDD 45 47 24 MAKE_BASE=TRUE 47 48 48 =PP1V05_S5_MCP 67 PP1V2R1V05_S5 49 241 mA max load 62 105 mA/241 mA 139 mA/ mA 68 (1.1V for A01) MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 49 76 79 =PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET 69 PPCPUVTT_S0 =PP1V8_GPUIFPX_REG 75 72 77 =PP1V8_GPU_IFPX =PP1V05_S0_CPU =PP1V05_S0_SMC_LS =PP1V05_S0_MCP_FSB 77 10 11 12 13 62 43 14 22 24 B =PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS 83 =PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDDQ =PP1V8_GPU_FBVDDQ =PP1V8_GPU_FBIO 18 19 21 25 64 27 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 73 74 73 74 71 72 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 21 24 24 25 64 =PPVTT_S0_DDR_LDO 78 46 PP0V9R0V75_S0_DDRVTT =PPVCORE_GPU_REG PPVCORE_GPU 21 22 24 54 58 59 =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP 39 68 45 69 82 =PP1V8_GPU_REG ENET Rails 45 =PP1V8_S0GPU_ISNS_R PP1V2R1V05_ENET 47 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_ENET_MCP_PLL_MAC 51 PP1V8_S0GPU_ISNS_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 32 48 71 29 OR 0.75V =PP1V05_ENET_FET =PPVCORE_GPU 28 32 34 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 25 80 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 81 Power Aliases 24 18 24 SYNC_MASTER=(MASTER) 33 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 34 =PP3V3_ENET_FET 83 PP3V3_ENET_PHY MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE =PP3V3_ENET_MCP_RMGT 18 24 =PP3V3_ENET_PHY 33 II NOT TO REPRODUCE OR COPY IT 22 24 46 86 =PP1V2_S0_REG PP1V2_S0 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE =PP1V2_S0_GMUX DRAWING NUMBER D 83 APPLE INC REV 051-7546 SCALE SHT NONE 75 PP1V8_GPUIFPX =PP2V5_S0_GMUX 75 45 86 PP2V5_S0 70 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 4500 mA 70 34 67 =PPCPUVTT_S0_REG 66 70 22 24 13 47 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V MAKE_BASE=TRUE 17 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE C 68 17 44 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 80 24 =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY =PP2V5_S0_REG 75 76 =PP3V3_GPU_LVDS_DDC 32 =PP3V3_S0_P1V2P2V5 =PP3V3_GPU_SMBUS_SMC_0_S0 =PP3V3_S0_TPAD 86 75 76 24 11 12 46 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON 50 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.00V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 48 80 =PP3V3_S0_BATTCHARGERTMPSNSR =PPVCORE_S0_MCP 68 PP1V05_S0_REG =PP1V05_S0_FET 69 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE =PPMCPCORE_S0_REG 32 69 52 67 11 12 45 36 38 47 =PP1V5_S0_MEM_A =PP1V5_S0_MEM_B =PP3V3_S0_GMUX =PP3V3_S0_DPMUX =PP3V3_S0_DPCONN =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_MCP_PLL_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP =PP3V3_S0_AUDIO =PP3V3_S0_ODD =PP3V3_S0_VMON =PP3V3_S0_SMBUS_MCP_1 =PP3V3_FC_CON 49 =PP3V3_FW_FWPHY =PP3V3_FW_P1V0FW =PPMCPDDR_ISNS_R =PP1V5_S0_CPU =PP1V5_S0_EXCARD =PP1V5_S0_VMON 47 PPVCORE_S0_CPU =PP3V3_FW_REG PPMCPDDR_ISNS 1182 mA Chipset "VCore" Rails 65 30 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE 29 =PP3V3_S0_SMBUS_MCP_0 =PPVCORE_S0_CPU 29 69 PP5V_S0 D 64 =PP1V5_FC_CON 81 38 28 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V MAKE_BASE=TRUE 37 38 69 PP1V8R1V5_S0_FET 28 =PP3V3_S0_EXCARD =PP3V3_S0_LVDSDDCMUX A =PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET 18 20 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE =PP1V8R1V5_S0_MCP_FET =PPVIN_S0_DDRREG_LDO =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET 69 69 =PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP =PP5V_S0_CPUVTTS0 =PP5V_S0_KBDLED =PP5V_S0GPU_P1V1P1V8_GPU =PP5V_S0_LPCPLUS =PP5V_S0_ODD =PP5V_S0_HDD =PPVCORE_S0_CPU_REG PP1V8R1V5_S3 51 69 PPVP_FW =PPBUS_S5_FW_FET 37 95 =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B 40 MIN_LINE_WIDTH=0.60 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE 62 18 25 MIN_LINE_WIDTH=0.8 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE 5300 mA 78 =PP5V_S3_P1V05S0FET =PP5V_S3_MCPDDRFET =PP5V_S3_VTTCLAMP =PP5V_S3_AUDIO_PWR =PP5V_RT_REG =PPDDR_S3_REG 64 69 64 =PP5V_S3_TPAD 65 PP3V3_S0 =PP3V3_S0_LPCPLUS =PP3V3_S0_SMC =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_MCPDDRISNS =PP3V3_S0_GPU1V8ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP =PP3V3_S0_PWRCTL =PP3V3_S0_DDC_LCD =PP3V3_S0_XDP =PP3V3_S0_MCPCOREISNS 60 PP5V_S3 =PP3V3R1V8_S0_MCP_IFP_VDD 44 53 30 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 61 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE B 190 mA 24 69 5V Rails 63 500 mA max supply 43 63 68 =PPMCPDDR_ISNS =PP3V3_FW_REG =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMS =PP3V3_S3_REMTHMSNS =PP3V3_S3_TPAD 61 PP3V42_G3H "FW" (FireWire) Rails PP1V8_S0 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE C PP3V3_S3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 23 44 24 16 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE =PP3V42_G3H_REG =PP1V8_S0_REG 67 82 =PPDCIN_S5_CHGR 60 95 60 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE =PP18V5_DCIN_CONN =PP3V3_S5_ROM =PP3V3_S5_MEMRESET =PP3V3_S3_P3V3S3FET =PP3V3_S5_LCD =PP3V3_S0_P3V3S0FET =PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05FET =PP3V3_S5_MCP =PP3V3_S5_MCP_GPIO =PP3V3_FW_LATEVG_ACTIVE 37 =PPVIN_S5_CPU_IMVP 60 =PP3V3_S5_MCP_A01 85 =PPVIN_S5_CPU_IMVP_ISNS_R =PPVIN_S0_P5VRTS0_MCPCORE =PPVIN_S3_DDRREG =PPVIN_S0GPU_P1V8P1V1 =PPVBAT_G3H_P3V42G3H =PPVIN_S0_P1V05S5 1.8V/DDR 1.5V Rails PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 66 =PPBUS_S5_FWPWRSW =PPVIN_GPU_GPUVCORE 46 =PP3V3_S5_REG 63 =PPVIN_S0_CPUVTTS0 =PPBUS_S0_LCDBKLT D 63 www.laptop-schematics.com A.0.0 OF 96 A CPU signals ZT0981 TP_IMVP6_CLKEN_L STDOFF-4.5OD.98H-1.1-3.48-TH ZT0984 ZT0985 STDOFF-4.5OD.98H-1.1-3.48-TH ZT0983 STDOFF-4.5OD.98H-1.1-3.48-TH D Right CPU TM Hole MEM_VTT_EN 26 TP_USB_EXTDN ZT0930 =MCP_BSEL 14 =DDRVTT_EN 64 69 STDOFF-4.5OD.98H-1.1-3.48-TH 20 90 TP_USB_MINIP USB_MINI_P 20 90 USB_MINI_N 20 90 MAKE_BASE=TRUE =SPI_CS1_R_L_USE_MLB 21 44 TP_USB_MININ MAKE_BASE=TRUE GPU signals PEG_D2R_P 89 70 =PEG_D2R_P 17 =PEG_D2R_N 17 D MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 PEG_D2R_N 89 70 PEG_R2D_C_P 89 70 PEG_R2D_C_N 17 =PEG_R2D_C_N 17 83 GMUX_INT =DVI_HPD_GMUX_INT 18 MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH =PEG_R2D_C_P MAKE_BASE=TRUE SM ZT0987 89 70 MAKE_BASE=TRUE SH0901 20 90 USB_EXTD_N MAKE_BASE=TRUE MAKE_BASE=TRUE ZT0986 USB_EXTD_P MAKE_BASE=TRUE MAKE_BASE=TRUE TP_SPI_CS1_R_L_USE_MLB STDOFF-4.5OD.98H-1.1-3.48-TH ZT0980 SH0903 STDOFF-4.5OD.98H-1.1-3.48-TH 2.0DIA-TALL-EMI-MLB-M97-M98 Bottom Left GPU TM Hole TP_USB_EXTDP 62 62 87 MAKE_BASE=TRUE SM SM Left CPU TM Hole CPU_BSEL 87 10 2.0DIA-TALL-EMI-MLB-M97-M98 STDOFF-4.5OD.98H-1.1-3.48-TH Top GPU Right TM Hole SH0900 SM IMVP6_VID MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 STDOFF-4.5OD.98H-1.1-3.48-TH ZT0982 VR_PWRGD_CLKEN_L MAKE_BASE=TRUE CPU_VID 87 11 SH0902 PCIE_CLK100M_FC_P 95 32 TP_PCIE_CLK100M_PE4P R0903 17 MAKE_BASE=TRUE 21 PCIE_CLK100M_FC_N TP_PCIE_CLK100M_PE4N 17 TP_PCIE_PE4_R2D_CP 17 TP_PCIE_PE4_R2D_CN 17 FC_CLKREQ_L 32 1.4DIA-SHORT-EMI-MLB-M97-M98SH0911 MAKE_BASE=TRUE SM 1.4DIA-SHORT-EMI-MLB-M97-M9832 FC_PRSNT_L SM TP_PE4_CLKREQ_L 17 TP_PCIE_PE4_D2RP 95 32 MCP_SPKR PCIE_FC_R2D_C_P 95 32 SMC_MCP_SAFE_MODE 42 5% 1/16W MF-LF 402 MAKE_BASE=TRUE MAKE_BASE=TRUE R0900 Frame Holes 10 =PP1V8_GPU_FB_VDDQ 3R2P5 61 60 MAKE_BASE=TRUE 1% 1/16W MF-LF 402 ZT0915 GND_BATT_CHGND SH0910 GPU_FB_A_VREF_DIV =PP1V8_GPU_FB_VREF_A R0901 1.4DIA-SHORT-EMI-MLB-M97-M98 MAKE_BASE=TRUE 1% 1/16W MF-LF 402 =PP1V8_GPU_FB_VREF_B SM 74 17 TP_USB_EXTCP TP_USB_EXTCN 17 PCIE_FC_D2R_N 95 32 TP_PCIE_PE4_D2RN TP_CPU_PECI_MCP 17 TP_MCP_GPIO_17 PCIE_RESET_L 26 17 LCD_BKLT_EN 83 LVDS_BKL_ON 85 DP_IG_ML_P 89 80 =MCP_HDMI_TXC_P 18 =MCP_HDMI_TXC_N 18 Extra FSB Pull-ups GND_CHASSIS_USB DP_IG_ML_N DP_IG_ML_P 89 80 24 22 14 HDA_BITCLK DP_IG_ML_N DP_IG_DDC_CLK HDA_BIT_CLK =MCP_HDMI_TXD_P 18 =MCP_HDMI_TXD_N 18 =PP5V_S3_AUDIO_PWR =MCP_HDMI_DDC_CLK 18 DP_IG_DDC_DATA =MCP_HDMI_DDC_DATA 18 NO STUFF NO STUFF R09501 R09701 R09901 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 220 200 NO STUFF ZT0965 R0960 3R2P5 GND_CHASSIS_CLUTCH 62 5% 1/16W MF-LF 402 ZT0960 3R2P5 GND_CHASSIS_SATA ZT0990 3R2P5 87 62 14 10 OUT 87 14 10 OUT 87 14 13 10 OUT 87 14 10 OUT 87 14 10 OUT Bosses for VRAM HS DP_IG_HPD 150 =MCP_HDMI_HPD 18 ALL_EG_PGOOD 83 MAKE_BASE=TRUE PM_ALL_GPU_PGOOD 68 MAKE_BASE=TRUE ZT0951 4.0OD1.65H-M1.6X0.35 TP_LVDS_MUX_SEL_EG LVDS_MUX_SEL_EG 83 EG_RESET_L 83 GPU_RESET_L 70 R0980 ZT0952 150 1% 1/16W MF-LF 402 4.0OD1.65H-M1.6X0.35 83 JTAG_GMUX_TDI 83 JTAG_GMUX_TMS GMUX_JTAG_TDI 19 GMUX_JTAG_TMS 19 MAKE_BASE=TRUE MAKE_BASE=TRUE JTAG_GMUX_TDO 83 GMUX_JTAG_TDO LVDS_IG_BKL_ON 18 17 MAKE_BASE=TRUE ZT0953 4.0OD1.65H-M1.6X0.35 IG_BKLT_EN 83 IG_LCD_PWR_EN 83 MAKE_BASE=TRUE LVDS_IG_PANEL_PWR 18 57 AUD_IPHS_SWITCH_EN 19 59 MAKE_BASE=TRUE =P3V3ENET_EN 34 34 CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V ETHERNET ALIASES MAKE_BASE=TRUE PP5V_S3_AUDIO_AMP 10K 54 56 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 5% 1/16W MF-LF 402 MAKE_BASE=TRUE NO STUFF C 21 90 PP5V_S3_AUDIO XW0901 R0902 MAKE_BASE=TRUE NO STUFF SM MAKE_BASE=TRUE 80 76 32 MAKE_BASE=TRUE MAKE_BASE=TRUE =PP1V05_S0_MCP_FSB SL-3.1X2.7-6CIR-NSP 17 XW0900 SM MAKE_BASE=TRUE 89 80 80 76 GND_CHASSIS_FAN 54 MAKE_BASE=TRUE Exist in MRB but not Intel designs Here for CYA If found to be necessary, will move to page14.csa ZT0950 TH 14 AUDIO ALIASES MAKE_BASE=TRUE 89 80 FC_RESET_L MAKE_BASE=TRUE MAKE_BASE=TRUE 20 90 MAKE_BASE=TRUE 3R2P5 20 90 USB_EXTC_N GMUX ALIASES GND_CHASSIS_LVDS ZT0945 USB_EXTC_P CPU_PECI_MCP AUD_IP_PERIPHERAL_DET MAKE_BASE=TRUE MAKE_BASE=TRUE SH0913 3R2P5 C 29 SM ZT0940 28 MEM_B_A MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 MEM_A_A MAKE_BASE=TRUE PCIE_FC_D2R_P MAKE_BASE=TRUE SH0912 GPU_FB_B_VREF_DIV TP_PE4_PRSNT_L TP_MEM_B_A MAKE_BASE=TRUE MAKE_BASE=TRUE 95 32 10 TP_MEM_A_A MAKE_BASE=TRUE MAKE_BASE=TRUE 73 PCIE_FC_R2D_C_N 95 32 MAKE_BASE=TRUE PM_SLP_RMGT_L 21 MAKE_BASE=TRUE =P1V05ENET_EN 33 =PP3V3_ENET_PHY_VDDREG 33 =RTL8211_REGOUT www.laptop-schematics.com Thermal Module Holes TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT MAKE_BASE=TRUE =RTL8211_ENSWREG 33 GND_CHASSIS_BATTCONN B B MCP79 PCIe PRSNT# Straps ZT0931 STDOFF-4.0OD3.0H-TH VENICE ZT0934 MAKE_BASE=TRUE STDOFF-4.0OD3.0H-TH NC_LVDS_B_DATAN NC_LVDS_A_DATAP STDOFF-4.0OD3.0H-TH NC_LVDS_A_DATAN ZT0935 1 VENICE LVDS_A_DATA_P LVDS_A_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_BKL_PWM PCIE_FW_PRSNT_L 5% 1/16W MF-LF 402 18 89 18 89 NC_LVDS_IG_A_DATAN LVDS_IG_A_DATA_N 18 89 LVDS_IG_B_DATA_P 18 89 LVDS_IG_B_DATA_N 18 89 MAKE_BASE=TRUE ZT0989 OUT GND 17 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.09MM VOLTAGE=0V R0926 EG_CLKREQ_OUT_L MCP_MII_PD =MCP_MII_RXER 18 =MCP_MII_CRS 18 =MCP_MII_COL 18 MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH NC_LVDS_IG_B_DATAP IN 83 5% 1/16W MF-LF 402 MAKE_BASE=TRUE A 18 89 Digital Ground PEG_PRSNT_L MAKE_BASE=TRUE ZT0988 LVDS_IG_A_DATA_P 17 NO STUFF 5% 1/16W MF-LF 402 NC_LVDS_IG_A_DATAP OUT MAKE_BASE=TRUE R0927 18 MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH Signal Aliases SYNC_MASTER=(MASTER) MAKE_BASE=TRUE NC_LVDS_IG_B_DATAN ZT0991 R0930 MAKE_BASE=TRUE NC_LVDS_A_DATAP NC_LVDS_A_DATAN LVDS_A_DATA_P LVDS_A_DATA_N 5% 1/16W MF-LF 402 MAKE_BASE=TRUE SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 47K STDOFF-4.5OD.98H-1.1-3.48-TH 20 Add other PRSNT# straps if needed R0925 NO_TEST=TRUE TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE TP_LVDS_IG_B_CLKN MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM STDOFF-4.0OD3.0H-TH LVDS_B_DATA_N These need work NO_TEST=TRUE MAKE_BASE=TRUE ZT0933 STDOFF-4.0OD3.0H-TH NO_TEST=TRUE MAKE_BASE=TRUE VENICE LVDS_B_DATA_P 20 =PP1V05_S0_MCP_SATA_AVDD1 NO_TEST=TRUE MAKE_BASE=TRUE ZT0932 NC_LVDS_B_DATAP =PP1V05_S0_MCP_SATA_DVDD1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT NC_LVDS_B_DATAP NC_LVDS_B_DATAN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART LVDS_B_DATA_P LVDS_B_DATA_N MAKE_BASE=TRUE SIZE DRAWING NUMBER D MAKE_BASE=TRUE APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 96 A OMIT BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 C BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 IN 87 14 OUT 87 14 IN 87 14 IN 87 14 IN 87 14 87 14 IN IN FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A20M* A5 FERR* C4 IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 F1 FSB_BREQ0_L CPU_IERR_L CPU_INIT_L IN BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 =PP1V05_S0_CPU IERR* INIT* D20 B3 LOCK* H4 FSB_LOCK_L RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 87 14 87 BI 10 11 12 13 62 R1002 54.9 1% 1/16W MF-LF 402 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY D 14 87 14 87 IN 13 14 87 IN 14 87 IN 14 87 IN 14 87 IN 14 87 OMIT A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 BR0* FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L 14 87 BI STPCLK* LINT0 LINT1 SMI* XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L BI 14 87 BI 14 87 BI 13 87 BI 13 87 BI 13 87 BI 13 87 BI 13 87 =PP1V05_S0_CPU R10031 87 14 BI 87 14 BI 1% 1/16W MF-LF 402 87 14 BI 87 14 BI 87 14 BI 87 14 BI 54.9 13 87 10 13 87 87 14 BI IN 10 13 87 87 14 BI 10 87 87 14 BI IN 10 13 87 87 14 BI IN 10 13 87 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI 87 14 BI OUT OUT 13 26 R1004 5% 1/16W MF-LF 402 THERMAL THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 D21 A24 B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 48 95 OUT 48 95 OUT 14 43 87 H CLK BCLK0 BCLK1 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N IN 14 87 IN 14 87 62 13 12 11 10 14 43 62 87 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) =PP1V05_S0_CPU R1005 1K 1% 1/16W MF-LF 402 R1020 87 13 10 XDP_TDI D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* BI R10061 XDP_TMS N22 FSB_D_L K25 FSB_D_L P26 FSB_D_L 87 14 BI R23 FSB_D_L 87 14 BI L23 FSB_D_L 87 14 BI M24 FSB_D_L 87 14 BI L22 FSB_D_L 87 14 BI M23 FSB_D_L 87 14 BI P25 FSB_D_L 87 14 BI P23 FSB_D_L 87 14 BI P22 FSB_D_L 87 14 BI T24 FSB_D_L 87 14 BI R24 FSB_D_L 87 14 BI L25 FSB_D_L 87 14 BI T25 FSB_D_L 87 14 BI N25 FSB_D_L 87 14 BI FSB_DSTB_L_N L26 87 14 BI FSB_DSTB_L_P M26 87 14 BI N24 FSB_DINV_L 87 14 BI 0.5" MAX LENGTH FOR CPU_GTLREF AD26 87 27 CPU_GTLREF C23 CPU_TEST1 D25 CPU_TEST2 C24 TP_CPU_TEST3 AF26 CPU_TEST4 AF1 TP_CPU_TEST5 NOSTUFF A26 TP_CPU_TEST6 C1000 0.1uF C3 TP_CPU_TEST7 10% 16V B22 CPU_BSEL 87 OUT X5R 402 B23 CPU_BSEL 87 OUT C21 CPU_BSEL 87 OUT BI IN B 87 13 10 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* 87 14 BI 54.9 R1021 54.9 2.0K =PP1V05_S0_CPU 10 11 12 13 62 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND R1024 54.9 XDP_TDO 87 10 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 87 14 68 PROCHOT* THERMDA THERMDC 10 11 12 13 62 87 14 BI 87 14 BI 87 13 10 XDP_TRST_L 649 OF MISC Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AF24 AC20 COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 87 87 87 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 BI 14 87 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1018 R1019 1% 1/16W MF-LF 402 54.9 CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L R1017 54.9 IN 14 62 87 IN 14 87 IN 14 87 IN 13 14 87 IN 14 87 OUT B 27.4 1% 1/16W MF-LF 402 62 54.9 R1023 FCBGA D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* R1030 R1022 XDP_TCK PENRYN NOSTUFF MF-LF 402 87 13 10 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 NOSTUFF R10121 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF R1007 1K 5% 1/16W MF-LF 402 CPU FSB SYNC_MASTER=M87_MLB A SYNC_DATE=10/17/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7546 SCALE SHT NONE www.laptop-schematics.com BI 87 14 H5 F21 E1 BI DATA GRP 87 14 DEFER* DRDY* DBSY* FSB_ADS_L FSB_BNR_L FSB_BPRI_L DATA GRP BI H1 E2 G5 DATA GRP BI 87 14 ADS* BNR* BPRI* DATA GRP BI 87 14 CONTROL 87 14 XDP/ITP SIGNALS BI A3* A4* PENRYN FCBGA A5* OF A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 87 14 U1000 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI ICH BI 87 14 RESERVED D 87 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 A.0.0 OF 10 96 A D D =PPVIN_S0GPU_P1V8P1V1 CRITICAL C9545 CRITICAL 1UF 22UF 10% 25V X5R 603-1 20% 25V POLY-TANT CASE-D2-SM C9590 Q9510 CRITICAL SI7904BDN PWRPK-1212-8 4.7 5% 1/16W MF-LF 402 D G P1V1GPU_DRVH MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE S 10% 25V X5R 805 C9501 1UF 10% 10V X5R 402-1 (Internal 10-ohm path from PVCC to VCC) PP5V_S0GPU_P1V1P1V8_VCC Q9510 CRITICAL PWRPK-1212-8 =PP5V_S0GPU_P1V1P1V8_GPU C9500 10UF SI7904BDN 10% 25V X5R 603-1 20% 25V POLY-TANT CASE-D2-SM PVIN_S0GPU_P1V1 C9595 1UF 22UF R9500 CRITICAL Q9560 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V D FDMS9600S =PP1V1_S0GPU_REG C9530 10% 50V X7R 603-1 L9510 3.3UH-3.5A 1 XW9515 SM 0.1UF CRITICAL CRITICAL 330UF C9510 P1V1GPU_VBST MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM P1V1GPU_LL MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE PCMB053T 20% 2.0V POLY-TANT B2-SM C9515 P1V1GPU_VFB P1V1GPU_TRIP PLACEMENT_NOTE=Place XW9515 next to C7615 10UF 20% 6.3V X5R 603 17 15 16 18 10 14 11 12 29 20 LDO VIN LDOREFIN BOOT1 CRITICAL BOOT2 UGATE1 UGATE2 PHASE1 ISL6236 PHASE2 LGATE1 LGATE2 QFN OUT1 OUT2 EN1 EN2 BYP FB1 REFIN2 ILIM1 ILIM2 SKIP* EN_LDO REF SECFB POK1 TON POK2 U9500 P1V1S0_VSNS R9520 5.76K B 1% 1/16W MF-LF 402 R9521 21 33 THRM_PAD GND 24 26 25 23 30 27 13 28 MMD06CZ-SM CRITICAL C9560 220UF MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM P1V8FB_DRVL (=PP1V8FB_S0_REG) C9580 10UF 20% 6.3V X5R 603 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE VOLTAGE=2V R95631 1% 1/16W MF-LF 402 Q2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE P1V8FB_LL PP2V_S0GPU_P1V8_REF 130K 20% 2.5V POLY-TANT CASE-B2-SM2 10% 50V X7R 603-1 GPU_P1V8_REFIN P1V8FB_TRIP R95851 XW9500 SM 280K Vout = 0.7V * (1 + Ra / Rb) (Rb should be between 10K and 100K) Vout = 1.8V 6A max output (Q9560 limit?) f = 300 kHz C9565 XW9565 SM P1V8_GPU_VSNS PLACEMENT_NOTE=Place next to C7665 14.0K 1% 1/16W MF-LF 402 R9535 1% 1/16W MF-LF 402 10 SW P1V8FB_VBST PGND 5% 50V CERM 402 Q1 (SGND) 100PF L9560 0.1UF 32 31 =PP1V8_GPU_REG CRITICAL 2.2UH-14A NC NO STUFF C9520 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE 10% 10V X5R 402-1 10% 10V X5R 402-1 P1V8FB_DRVH 1UF 1UF PVCC VCC VREF3 Vout = 1.103V 3A max output (Q9510 limit?) f = 400 kHz C9503 C9504 22 P1V1GPU_DRVL MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE 19 S G C MLP PP5V_S0GPU_VREF GND_P1V1P1V8_SGND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V C9585 0.1UF 20% 10V CERM 402 R95641 127K 1% 1/16W MF-LF 402 R9562 78.7K C9561 0.01UF 10% 16V CERM 402 1% 1/16W MF-LF GPUFB_VID_L Q9565 D SSM3K15FV SOD-VESM-HF 1% 1/16W MF-LF 402 IN 68 OUT 68 OUT 83 68 67 IN C B 402 10K 83 68 www.laptop-schematics.com C9540 =P1V1GPU_EN P1V1GPU_PGOOD P1V8FB_PGOOD =P1V8FB_EN S G GPIO7_FBVDD_ALTVO 76 1.1V / 1V8 FB Power Supply SYNC_MASTER=MUXGFX A SYNC_DATE=07/10/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 82 96 A 83 =PP3V3_S0_GMUX C9610 0.1UF C9621 0.1UF 20% 10V CERM 402 C9622 1 0.1UF 20% 10V CERM 402 C9623 0.1UF 20% 10V CERM 402 C9624 0.1UF 20% 10V CERM 402 C9625 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9626 0.1UF 20% 10V CERM 402 C9628 0.1UF 20% 10V CERM 402 C9629 0.1UF 20% 10V CERM 402 89 83 18 C9630 0.1UF 89 83 18 20% 10V CERM 402 89 83 18 89 83 18 89 83 18 FERR-220-OHM =PP2V5_S0_GMUX PP3V3_S0_ULC_F D C9611 1 0.1UF C9612 0.1UF 20% 10V CERM 402 C9613 0.1UF 20% 10V CERM 402 C9614 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9615 0.1UF 20% 10V CERM 402 C9616 0.1UF 20% 10V CERM 402 C9631 C9617 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 89 83 18 89 83 18 0.1UF 0.1UF 94 83 77 20% 10V CERM 402 20% 10V CERM 402 L9627 94 83 77 FERR-220-OHM 94 83 77 94 83 77 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 0402 94 83 77 94 83 77 =PP1V2_S0_GMUX LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P R9650 R9651 R9652 R9653 R9654 R9655 R9656 100 100 100 100 2 2 100 100 100 2 100 100 100 100 100 100 100 C9627 94 83 77 LVDS_EG_A_CLK_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P R9660 R9661 R9662 R9663 R9664 R9665 R9666 4.7UF 20% 4V X5R 402 C9604 0.1UF C9605 0.1UF 20% 10V CERM 402 C9606 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9607 0.1UF 20% 10V CERM 402 C9608 20% 10V CERM 402 C9609 0.1UF 0.1UF 20% 10V CERM 402 83 GMUX_CFG0 2 2 2 1% 1/16W MF-LF 402 83 80 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 83 OUT 76 OUT 79 OUT 90 44 42 19 BI BI 90 44 42 19 BI 90 44 42 19 BI 90 44 42 19 BI 90 26 19 IN 26 83 B 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN 10K 89 83 18 IN 1% 1/16W MF-LF 402 89 83 18 IN R9647 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN 89 83 18 IN OUT IN 83 IN IN 83 IN (Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU) PL2A PL2B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B PL16A PL16B PL18A PL18B PL19A PL19B PL32A PL32B GND J1 PM_SLP_S3_L Isolation 83 =PP3V3_S0_GMUX A Q9670 K12 A4 P11 ULC_VCCPLL LRC_VCCPLL VCCIO7 VCCIO6 VCCIO5 VCCIO4 VCCIO3 B5 B7 A12 C14 F13 M12 M9 M3 N5 M1 C3 F2 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N A2 A3 A1 B3 C5 A5 B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13 LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N EG_PWRSEQ_EN GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N TP_GMUX_PT20A TP_GMUX_PT20B TP_GMUX_PT32A TP_GMUX_PT32B PR2A PR2B PR10A PR10B PR11A PR11B PR12A PR12B PR13A PR13B PR14A PR14B PR15A PR15B PR16A PR16B PR18A PR18B PR30A PR30B A14 B14 D12 D13 D14 E14 E12 F12 F14 G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13 DP_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N IG_LCD_PWR_EN EG_LCD_PWR_EN IG_BKLT_EN EG_BKLT_EN OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 1K JTAG_GMUX_TCK R9690 4.7K EG_CLKREQ_OUT_L NO STUFF R9695 10K 83 80 83 80 83 80 80 94 IN 83 IN 83 18 83 89 18 83 89 18 83 89 18 83 89 18 83 89 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 LVDS_EG_A_CLK_N LVDS_EG_A_DATA_N LVDS_EG_A_DATA_N LVDS_EG_A_DATA_N D 18 83 89 LVDS_EG_B_DATA_N LVDS_EG_B_DATA_N LVDS_EG_B_DATA_N 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 =PP3V3_S0_GMUX 10K 1% 1/16W MF-LF 402 PLACEMENT_NOTE=Place on top side at U9200 DP_MUX_SEL_EG R9681 10K C LVDS_DDC_SEL_IG R9682 10K LVDS_DDC_SEL_EG R9683 10K 5% 1/16W MF-LF 402 5% 1/16W 5% 1/16W MF-LF 402 MF-LF 402 (Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid) OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 OUT 80 94 83 83 84 83 83 NO STUFF EG_RESET_L R9691 100K GMUX_INT R9692 20K LCD_BKLT_PWM R9693 100K EG_CLKREQ_IN_L R9694 R9630 100K EG_PWRSEQ_HW 5% IN 76 80 81 IN 80 IN 77 83 94 IN 77 83 94 EG_RAIL1_EN EG_PWRSEQ_GMUX R9631 EG_RAIL2_EN EG_PWRSEQ_GMUX R9632 83 EG_RAIL3_EN EG_PWRSEQ_GMUX R9633 83 EG_RAIL4_EN R9634 83 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN 77 83 94 IN IN 76 IN IN 76 5% 5% 5% 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 EXTGPU_PWR_EN OUT 1/16W MF-LF 402 1/16W MF-LF 402 68 =P1V1GPU_EN OUT 68 82 P3V3GPU_EN OUT 68 69 1/16W MF-LF 402 =GPUVCORE_EN 1/16W MF-LF 402 OUT B 68 78 EG_PWRSEQ_GMUX =P1V8FB_EN OUT 67 68 82 5% 1/16W MF-LF 402 The MAKE BASE properties for these signals are on the POWER CONTROL page NO STUFF NO STUFF C9691 0.1UF C9693 0.1UF 20% 10V CERM 402 20% 10V CERM 402 NO STUFF C9692 NO STUFF 0.1UF C9694 0.1UF 20% 10V CERM 402 20% 10V CERM 402 Graphics MUX (GMUX) GMUX_JTAG_TCK Inversion JTAG_GMUX_TCK SYNC_MASTER=MUXGFX G S R9670 EG_PWRSEQ_EN 10K SYNC_DATE=07/10/2008 1% 1/16W MF-LF 402 GMUX_PM_SLP_S3_L MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY 83 TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION D IC,XP2-8,HF,CPLD,BLANK U9600 CRITICAL GMUX_8K_BLANK 341S2350 IC,CPLD,LATTICE,132CSBGA,M98 U9600 CRITICAL GMUX_PROG Q9670 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SSM6N15FEAPE TABLE_5_ITEM 336S0027 SOT563 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_5_ITEM 83 II NOT TO REPRODUCE OR COPY IT S G III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART GMUX_JTAG_TCK_L IN SIZE 17 DRAWING NUMBER D APPLE INC REV 051-7546 SCALE SHT NONE 18 83 89 1 PM_SLP_S3_L IN D SOT563 R9680 SILK_PART=GMUX_RST PT2A PT2B PT3A PT3B PT4A PT4B PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT32A PT32B 83 SSM6N15FEAPE 42 37 34 21 81 68 44 BANK6 26 B1 B2 C2 D3 D1 E1 D2 E3 F1 G1 F3 G2 H2 G3 H1 H3 L1 L3 K3 L2 N1 P1 1% LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N R96791 83 LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N TP_GMUX_PL10A TP_GMUX_PL10B LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_MUX_SEL_EG TP_GMUX_PL18B_VSYNC =GMUX_PCIE_RESET_L GMUX_PM_SLP_S3_L ALL_EG_PGOOD EG_CLKREQ_IN_L BANK7 NO STUFF IN OUT BANK4 90 44 42 19 BANK0 10K OUT 402 Required Pulldowns CSBGA-HF BANK5 10K 1% 1/16W MF-LF 402 OUT 80 PB2A PB2B PB14A PB14B PB15A (OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B (OD) PB19A PB19B PB20A PB20B PB30A PB30B PB31A PB31B PB32A PB32B BANK1 R9646 OUT 83 80 GMUX_DEBUG_RESET_L U9600 CFG0 BANK2 R9641 NO STUFF OUT 83 80 83 XP28 P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9 N9 P10 M10 P12 P13 N12 P14 BANK3 84 83 K1 LCD_BKLT_EN LCD_BKLT_PWM LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG DP_MUX_EN DP_MUX_SEL_EG EG_RESET_L EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_CLKREQ_OUT_L DP_CA_DET_EG LCD_PWR_EN LPC_AD LPC_AD LPC_AD LPC_AD LPC_FRAME_L LPC_RESET_L LPC_CLK33M_GMUX GMUX_INT ULC_GNDPLL LRC_GNDPLL NO STUFF OUT B4 M11 VCCJ OMIT CRITICAL GNDIO7 C VCCIO2 IN GNDIO6 TCK TDI TDO TMS TOE VCCIO1 OUT K14 L13 K13 L12 K2 GNDIO5 JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS GMUX_TOE GNDIO3 GNDIO4 IN GNDIO2 83 GNDIO1 1% 1/16W MF-LF 402 GNDIO0 10K B8 C6 C12 C13 E13 M14 N10 N6 P3 M2 C1 E2 R9645 10K 1% 1/16W MF-LF 402 VCCIO0 C11 J2 J14 M8 B11 C4 J3 J13 N11 P8 R9640 VCCAUX 402 MF-LF Required Pullups 20% 10V CERM 402 VCC MF-LF 1/16W SIGNAL_MODEL=EMPTY 83 1/16W 1% 0.1UF C9600 1% 0402 PP3V3_S0_LRC_F PLACEMENT_NOTE=Place at U9200 (All 14 resistors) 83 L9631 LVDS Receiver Termination GMUX CPLD =PP3V3_S0_GMUX www.laptop-schematics.com A.0.0 OF 83 96 A *Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER *BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE CRITICAL PLACEMENT_NOTE=Place near Q9701 PLACEMENT_NOTE=Place near C9710 DO222-SM PLACEMENT_NOTE=Place near J9000 L9701 D9701 22UH-2.5A VOLTAGE=12.6V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.4 mm D PPVIN_S0_LCDBKLT_BUF VOLTAGE=12.6V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM R9730 0.1 1% 1/6W MF 402-HF PPVOUT_S0_LCDBKLT_SW VOLTAGE=30V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm SWITCH_NODE=TRUE IHLP2525CZ-SM R9701 100 1% CRITICAL 10UF CRITICAL 1/16W MF-LF 402 C9701 D PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW 10% 25V X5R 805 BOOST_FET_CNTL BKL_VIN GND_BKL_PWRGND 2.2UF 10% 100V X7R 1210 SSOT6 S 2.2UF 10% 100V X7R 1210 PLACEMENT_NOTE=Place near C9709 C9702 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM 10% 25V X5R 402 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM PLACEMENT_NOTE=Place near C9701 CRITICAL C9709 C9710 Q9701 FDC5612 G 0.1UF GND_BKL_PWRGND 84 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.6MM PLACEMENT_NOTE=Place near L9701 XW9701 SM D STPS1H100MF PLACEMENT_NOTE=Place near Q9701 BOOST_SINK GND_BKL_PWRGND 187K BKL_SYNC IN 1/16W MF-LF 402 C9713 10% 25V X5R 402 1/16W MF-LF 402 R9705 1/16W MF-LF 402 1/16W MF-LF 402 2 VSYNC ISWSEN ISEN1 2 C9712 PPVOUT_S0_LCDBKLT 47PF 5% 50V CERM 402 BKL_ISWSEN VOLTAGE=30V MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm NOSTUFF 1/16W MF-LF 402 ISEN2 BKL_RT RT ISEN3 12 BKL_ISEN3 BKL_SSTCMP SSTCMP ISEN4 14 BKL_ISEN4 20 DIM ISEN5 15 BKL_ISEN5 19 LPF ISEN6 16 BKL_ISEN6 C9714 1/16W MF-LF 402 BKL_LRT 18 1UF 0.0022UF 10% 50V CERM 402 10% 10V X5R 402 VSEN LRT GNDA NOSTUFF NOSTUFF BKL_SSTCMP_RC ISET 11 BKL_ISEN2 BKL_LPF 5% C9706 84 R9713 84 1 C9707 2.2UF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm NTUD3127CXXG 83 IN D 1/16W MF-LF 402 PPVOUT_S0_LCDBKLT PLACEMENT_NOTE=Away from Q9701 79 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 79 10.2 LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 79 10.2 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 79 OUT 79 B 10.2 LED_RETURN_1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 79 84 C9708 0.1UF 10% 25V X5R 402 R9723 1.2M 1% 1/10W MF-LF 603 R9711 30.1K 1% G S A OUT BKL_VSEN 1/16W MF-LF 402 LCD BACKLIGHT DRIVER R9724 SYNC_MASTER=YITE_M98_MLB 71.5K 1 1% 1/16W MF-LF 402 SYNC_DATE=07/02/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC *R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT C 10K 2 BKLT_PLL BKL_LRT_RC MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm SOT-963 LCD_BKLT_PWM 1% 1/16W MF-LF 402 LED_RETURN_4 0.1% 1/16W TF 402 R9727 N-CHN R9710 10.2 0.1% 1/16W TF 402 GND_BKL_PWRGND 2 Q9702 BKL_PWR_EN_L CRITICAL 20% 6.3V CERM 402-LF BKL_VREF_IN_4V9 1/16W MF-LF 402 P-CHN G D S 100K 1% MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 75K 1% 1/16W MF-LF 402 BKLT_PLL SOT-963 LED_RETURN_5 R9722 R9714 10K 5% BKLT_PLL_NOT NTUD3127CXXG R9700 79 R9720 THRM_PAD BKLT_PLL 1/16W MF-LF 402 Q9702 BKL_VREF_4V9 OUT R9719 PLACEMENT_NOTE=Away from Q9701 PLACEMENT_NOTE=Away from Q9701 84 10.2 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% CRITICAL MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9721 BKL_VREF_4V9 B LED_RETURN_6 R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm C9705 20% 16V CERM 402 10.2 0.1% 1/16W TF 402 0.01UF 79 84 OUT R9717 10 BKL_ISEN1 BKL_ISET BKL_DIM R9733 R9703 2.0M 5% 1/16W MF-LF 402 1 BKLT_PWM_RC R9709 ENA 13 2 PLACEMENT_NOTE=Away from Q9701 1/16W MF-LF 402 DRV MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACEMENT_NOTE=Away from Q9701 1K 1% U9701 QFN VREF GOSHAWK6P PLACEMENT_NOTE=Away from Q9701 R9708 VIN 17 100K 1% PLACEMENT_NOTE=Place near C9709 and Q9701 *R9702 AND R9715 PIN SHOULD BE PLACED NEAR C9709 PIN R9706 10K 5% 100K 1% 0.1UF 10% 10V X5R 402 GND_BKL_PWRGND_X MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM 1 C9703 1UF 3.01K 1% 1/6W MF 402 XW9702 SM BKL_VSYNC R9734 C 0.4 1% 1/6W MF 402 BKLT_PLL 79 5% R9707 R9715 0.4 1% 1% 1/16W MF-LF 402 BKL_VREF_4V9 R9702 21 85 84 84 BKLT_EN 1/16W MF-LF 402 R9731 PPBUS_S0_LCDBKLT_PWR R9704 100 1% 84 BKL_VREF_4V9 2 PLACEMENT_NOTE=Place near C9709 and Q9701 www.laptop-schematics.com PPBUS_S0_LCDBKLT_PWR IN 85 84 SCALE SHT NONE REV 051-7546 A.0.0 OF 84 96 A Q9806 FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET SSOT6-HF F9800 IN MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 0402-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V R9808 301K 2 FDC638APZ CHANNEL P-TYPE RDS(ON) D 43 mOhm @4.5V C9802 LOADING 0.1UF 1% 1/16W MF-LF 402 MOSFET 10% 16V X5R 402 0.4 A (EDP) D =PPBUS_S0_LCDBKLT 2AMP-32V PPBUS_S0_LCDBKLT_EN_DIV R9809 www.laptop-schematics.com 147K 1% 1/16W MF-LF 402 PPBUS_S0_LCDBKLT_EN_L Q9807 D SSM6N15FEAPE SOT563 85 IN G LVDS_BKL_ON PPBUS_S0_LCDBKLT_PWR S MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_EN_L Q9807 OUT 84 D SSM6N15FEAPE SOT563 C 26 IN G BKLT_PLT_RST_L C S B B LVDS_BKL_ON 85 R9840 4.7K 5% 1/16W MF-LF LCD Backlight Support 402 A SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 85 96 A 2.5V/1.2V S3 Switcher D =PP3V3_S0_P1V2P2V5 C9900 CRITICAL L9980 2.2UF 2.2UH-1.2A 20% 6.3V CERM 402-LF P1V2S0_SW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE 10PF 5% 50V CERM 402 C VIN LTC3547 U9900 DFN-HF 1% 1/16W MF-LF 402 20% 4V X5R 402 L9900 2.2UH-1.2A P2V5S0_SW =PP2V5_S0_REG PCAA031B-SM C9901 10PF 5% 50V CERM 402 P2V5S0_VFB R9900 475K 1% 1/16W MF-LF 402 68 C 4.7UF 1% 1/16W MF-LF 402 CRITICAL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE IN Vout = 1.2V 300mA max output (Switcher limit) f = 2.25 MHz C9985 280K RUN1 RUN2 280K R9983 SW1 GND R9982 P1V2S0_VFB CRITICAL VFB1 SW2 VFB2 THRML PAD =PP1V2_S0_REG PCAA031B-SM C9982 68 www.laptop-schematics.com D R9901 =P2V5S0_EN 150K Vout = 2.5V 0.3A max output (Switcher limit) f = 2.25 MHz C9905 4.7UF 20% 4V X5R 402 1% 1/16W MF-LF 402 =P1V2S0_EN Vout = 0.6V * (1 + Ra/Rb) B B Misc Power Supplies SYNC_MASTER=MUXGFX A SYNC_DATE=02/01/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 86 96 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_DATA * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR * TABLE_SPACING_RULE_ITEM ? =STANDARD FSB_ADDR TOP,BOTTOM ? =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM FSB_ADSTB * TABLE_SPACING_RULE_ITEM ? =2x_DIELECTRIC FSB_ADSTB TOP,BOTTOM ? =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM FSB_1X * TABLE_SPACING_RULE_ITEM ? =STANDARD FSB_1X TOP,BOTTOM ? =3x_DIELECTRIC All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 300 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 300 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Signals within each 1x group should be matched to CPU clock, +0/-1000 mils FSB 1X Signals Design Guide recommends each strobe/signal group is routed on the same layer Intel Design Guide recommends FSB signals be routed only on internal layers NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD C PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =50_OHM_SE =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_AGTL * =STANDARD ? CPU_8MIL * MIL ? TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM ? =2x_DIELECTRIC TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL ? CPU_GTLREF * 25 MIL ? TABLE_SPACING_RULE_ITEM SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * ? MIL SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_50S FSB_50S FSB_50S FSB_ADDR FSB_ADDR FSB_ADSTB FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_50S FSB_50S FSB_ADDR FSB_ADSTB FSB_A_L FSB_ADSTB_L FSB_1X FSB_BREQ0_L FSB_BREQ1_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L CPU_50S PM_DPRSLPVR (See above) CPU_50S CPU_50S CPU_AGTL CPU_AGTL PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5 CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N (FSB_CPURST_L) CPU_VCCSENSE CPU_VCCSENSE A (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_IERR_L 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 www.laptop-schematics.com TABLE_SPACING_RULE_HEAD FSB 4X Signal Groups TABLE_PHYSICAL_RULE_ITEM 10 14 10 14 10 14 10 14 10 14 10 14 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 C 10 14 10 13 14 10 14 10 14 10 14 10 10 14 10 14 10 14 10 14 10 14 10 14 43 62 10 13 14 10 14 10 14 10 14 43 10 14 10 14 10 14 62 10 14 14 14 14 14 10 14 10 14 B 13 14 13 14 14 14 10 21 62 62 10 27 10 10 10 10 10 13 10 10 13 10 13 10 13 10 13 10 13 13 11 CPU/FSB Constraints 62 11 62 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 11 62 NOTICE OF PROPRIETARY PROPERTY 62 62 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 87 96 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_A_CLK MEM_70D_VDD MEM_70D_VDD MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_70D_VDD MEM_70D_VDD MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 15 28 15 28 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * ? =2:1_SPACING 15 28 15 28 15 28 15 28 15 28 D 15 28 15 28 15 28 TABLE_SPACING_RULE_ITEM * =2.5:1_SPACING ? MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * ? =3:1_SPACING TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * ? =1.5:1_SPACING TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? MEM_DQS2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM 15 28 15 28 15 28 15 28 15 28 15 28 15 28 www.laptop-schematics.com MEM_CTRL2MEM 15 28 TABLE_SPACING_RULE_ITEM MEM_2OTHER * ? 25 MIL Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR2: B DQ signals should be matched within 20 ps of associated DQS pair DQS intra-pair matching should be within ps, no inter-pair matching requirement All DQS pairs should be matched within 100 ps of clocks CLK intra-pair matching should be within ps, inter-pair matching should be within 140 ps A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric DDR3: DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MCP MEM COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP * Y MIL MIL =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * MIL 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 C 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 29 15 29 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 15 28 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 A MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 B 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 Memory Constraints 15 29 15 29 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 15 29 NOTICE OF PROPRIETARY PROPERTY 15 29 15 29 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 16 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 88 96 A PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF 13.1 MM =90_OHM_DIFF =90_OHM_DIFF CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N MCP_PEX_CLK_COMP CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF TMDS_IG_TXC TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N DP_ML DP_ML DP_AUX_CH DP_AUX_CH DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_IG_ML_P DP_IG_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N MCP_HDMI_RSET MCP_HDMI_VPROBE MCP_DV_COMP MCP_DV_COMP LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_DV_COMP SATA_HDD_R2D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D TABLE_PHYSICAL_RULE_ITEM PEG_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * TABLE_SPACING_RULE_ITEM ? =3X_DIELECTRIC PEG_D2R PCIE TOP,BOTTOM ? =4X_DIELECTRIC TABLE_SPACING_RULE_ITEM D CLK_PCIE * 20 MIL ? MCP_PEX_COMP * MIL ? 70 70 70 70 70 70 70 70 D TABLE_SPACING_RULE_ITEM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_MINI_R2D Analog Video Signal Constraints PCIE_MINI_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER 31 95 31 95 17 31 17 31 17 31 17 31 TABLE_PHYSICAL_RULE_ITEM WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM CRT * TABLE_SPACING_ASSIGNMENT_ITEM ? =4:1_SPACING PCIE_FW_R2D SPACING_RULE_SET CRT CRT * CRT_2CRT PCIE_FW_D2R TABLE_SPACING_RULE_ITEM CRT_2CRT * ? =STANDARD TABLE_SPACING_RULE_ITEM CRT_2CLK * ? 50 MIL 36 36 17 36 17 36 www.laptop-schematics.com TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING 17 36 17 36 36 36 TABLE_SPACING_RULE_ITEM CRT_2SWITCHER * ? 250 MIL TABLE_SPACING_RULE_ITEM CRT_SYNC * ? 16 MIL PCIE_EXCARD_R2D TABLE_SPACING_RULE_ITEM MCP_DAC_COMP * ? =2:1_SPACING CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor - 50-ohm from first to second termination resistor - 75-ohm from output of three-pole filter to connector (if possible) R/G/B signals should be matched as close as possible and < 10 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2 PCIE_EXCARD_D2R MCP_PE0_REFCLK MCP_PE1_REFCLK C Digital Video Signal Constraints MCP_PE2_REFCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP MCP_PE3_REFCLK DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_PEX_CLK_COMP 32 95 32 95 17 32 17 32 17 32 17 32 17 70 17 70 17 31 17 31 C 17 36 17 36 17 32 17 32 17 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP * 20 MIL Y 20 MIL =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? DISPLAYPORT TOP,BOTTOM ? =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM LVDS * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? LVDS TOP,BOTTOM ? =4x_DIELECTRIC LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT SATA LAYER * =4x_DIELECTRIC ? SATA_TERMP * MIL ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM B TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM TABLE_SPACING_RULE_ITEM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 SATA_HDD_D2R SATA_ODD_R2D SATA_ODD_D2R A MCP_SATA_TERMP MCP_HDMI_RSET MCP_HDMI_VPROBE LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_TERMP SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N MCP_SATA_TERMP 18 25 18 25 18 25 18 25 18 25 18 25 18 25 80 80 18 80 18 80 18 25 18 25 18 83 18 83 B 18 83 18 83 18 18 18 18 18 83 18 83 18 18 18 25 18 25 20 39 20 39 39 39 20 39 20 39 39 39 20 39 20 39 39 MCP Constraints 39 20 39 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 20 39 NOTICE OF PROPRIETARY PROPERTY 39 39 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 20 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 89 96 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? CLK_PCI * MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT LPC LAYER * MIL ? CLK_LPC * MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MCP_DEBUG PCI_AD PCI_AD24 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI_55S CLK_PCI CLK_PCI PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L LPC_55S LPC_55S LPC_55S LPC LPC LPC LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_EXCARD_P USB_EXCARD_N USB_EXTC_P USB_EXTC_N SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 13 19 D 19 19 www.laptop-schematics.com TABLE_PHYSICAL_RULE_ITEM 19 19 19 42 44 83 19 42 44 83 19 26 83 TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB C * USB_EXTA TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 USB_MINI SMBus Interface Constraints USB_EXTD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_CAMERA TABLE_PHYSICAL_RULE_ITEM USB_BT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_TPAD TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? USB_IR SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 USB_EXTB HD Audio Interface Constraints USB_EXCARD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_EXTC 19 26 26 42 26 44 20 40 20 40 C 20 20 20 20 20 31 20 31 20 31 20 31 20 50 20 50 20 41 20 41 20 40 20 40 20 32 20 32 20 20 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP 21 CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK 26 42 SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L 20 TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? MCP_HDA_COMP * MIL ? TABLE_SPACING_RULE_ITEM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 B SIO Signal Constraints PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? HDA_SYNC TABLE_PHYSICAL_RULE_HEAD MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM CLK_SLOW * HDA_SDOUT SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 MCP_HDA_PULLDN_COMP SPI Interface Constraints MCP_SUS_CLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPI_CLK TABLE_PHYSICAL_RULE_ITEM SPI_MOSI TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? SPI_MISO TABLE_SPACING_RULE_ITEM SPI * SPI_CS0 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 13 21 45 13 21 45 21 45 21 45 21 B 21 21 54 21 21 21 54 21 54 21 54 21 21 26 21 44 44 53 21 44 44 53 21 44 53 21 44 MCP Constraints SYNC_MASTER=MUXGFX A SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 90 96 A MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S ENET_MII_55S MCP_BUF0_CLK MCP_BUF0_CLK MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_RXD ENET_RXD_STRAP ENET_RXD ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_TXCLK ENET_TXD0 ENET_TXD ENET_TXD ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP WEIGHT 18 18 18 34 33 34 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM 18 33 18 33 D 33 18 33 33 18 33 18 33 18 33 TABLE_SPACING_RULE_HEAD LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P ENET_MDI_N 18 33 18 33 18 33 www.laptop-schematics.com SPACING_RULE_SET 18 33 18 33 33 35 33 35 C C B B Ethernet Constraints SYNC_MASTER=MUXGFX A SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 91 96 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N 36 38 36 38 36 38 36 38 36 38 36 38 36 38 36 38 D D www.laptop-schematics.com Port Not Used C C B B FireWire Constraints SYNC_MASTER=MUXGFX A SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 92 96 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 45 45 45 45 45 45 45 45 D 45 45 SMBus Charger Net Properties NET_TYPE PHYSICAL SPACING CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N 61 61 61 www.laptop-schematics.com ELECTRICAL_CONSTRAINT_SET 61 C C B B SMC Constraints SYNC_MASTER=MUXGFX A SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 93 96 A GDDR3 Frame Buffer Signal Constraints GDDR3 FB A/B Net Properties GDDR3 FB C/D Net Properties TABLE_PHYSICAL_RULE_HEAD ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR3_40R55SE * =55_OHM_SE =40_OHM_SE 0.095 MM 12.7 MM =STANDARD =STANDARD GDDR3_40SE * =40_OHM_SE =40_OHM_SE 0.095 MM =40_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM FB_A_CLK_P PHYSICAL NET_TYPE SPACING GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK FB_AB_CMD GDDR3_40R55SE GDDR3_CMD TABLE_PHYSICAL_RULE_ITEM GDDR3_80D * =80_OHM_DIFF =80_OHM_DIFF 0.095 MM =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF FB_B_CLK_P FB_AB_CMD GDDR3_40R55SE GDDR3_CMD FB_AB_CMD GDDR3_40R55SE GDDR3_CMD FB_AB_CMD GDDR3_40R55SE GDDR3_CMD FB_AB_CMD GDDR3_40R55SE GDDR3_CMD FB_AB_CMD GDDR3_40R55SE GDDR3_CMD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR3_CLK * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_CMD * =2.5:1_SPACING ? GDDR3_DATA * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM FB_AB_CMD_PD GDDR3_40R55SE GDDR3_CMD FB_AB_CS0 GDDR3_40R55SE GDDR3_CMD FB_AB_CMD_PD GDDR3_40R55SE GDDR3_CMD FB_A_CMD GDDR3_40SE GDDR3_CMD FB_B_CMD GDDR3_40SE GDDR3_CMD FB_A_WDQS0 GDDR3_40SE GDDR3_DQS TABLE_SPACING_RULE_ITEM GDDR3_DQS * =2.5:1_SPACING ? From T18 MXM: Digital Video Signal Constraints FB_A_WDQS1 GDDR3_40SE GDDR3_DQS FB_A_WDQS2 GDDR3_40SE GDDR3_DQS FB_A_WDQS3 GDDR3_40SE GDDR3_DQS FB_A_RDQS0 GDDR3_40SE GDDR3_DQS FB_A_RDQS1 GDDR3_40SE GDDR3_DQS FB_A_RDQS2 GDDR3_40SE GDDR3_DQS FB_A_RDQS3 GDDR3_40SE GDDR3_DQS FB_A_DQ_BYTE0 GDDR3_40SE GDDR3_DATA FB_A_DQ_BYTE1 GDDR3_40SE GDDR3_DATA FB_A_DQ_BYTE2 GDDR3_40SE GDDR3_DATA FB_A_DQ_BYTE3 GDDR3_40SE GDDR3_DATA FB_A_DQM0 GDDR3_40SE GDDR3_DATA FB_A_DQM1 GDDR3_40SE GDDR3_DATA FB_A_DQM2 GDDR3_40SE GDDR3_DATA FB_A_DQM3 GDDR3_40SE GDDR3_DATA FB_B_WDQS0 GDDR3_40SE GDDR3_DQS FB_B_WDQS1 GDDR3_40SE GDDR3_DQS FB_B_WDQS2 GDDR3_40SE GDDR3_DQS FB_B_WDQS3 GDDR3_40SE GDDR3_DQS FB_B_RDQS0 GDDR3_40SE GDDR3_DQS FB_B_RDQS1 GDDR3_40SE GDDR3_DQS FB_B_RDQS2 GDDR3_40SE GDDR3_DQS FB_B_RDQS3 GDDR3_40SE GDDR3_DQS FB_B_DQ_BYTE0 GDDR3_40SE GDDR3_DATA TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM C DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N FB_A_MA FB_A_MA FB_A_BA FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_CKE FB_A_CS0_L FB_A_DRAM_RST FB_A_LMA FB_A_UMA FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_C_CLK_P 72 73 72 73 FB_D_CLK_P 72 73 72 73 PHYSICAL SPACING GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK GDDR3_80D GDDR3_CLK FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N 72 74 72 74 72 74 72 74 FB_B_MA FB_B_MA FB_B_BA FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_CKE FB_B_CS0_L FB_B_DRAM_RST 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD_PD GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CS0 GDDR3_40R55SE GDDR3_CMD 72 73 FB_CD_CMD_PD GDDR3_40R55SE GDDR3_CMD 72 73 FB_C_CMD GDDR3_40SE GDDR3_CMD 72 73 FB_D_CMD GDDR3_40SE GDDR3_CMD 72 73 FB_C_WDQS0 GDDR3_40SE GDDR3_DQS 72 73 FB_C_WDQS1 GDDR3_40SE GDDR3_DQS 72 73 FB_C_WDQS2 GDDR3_40SE GDDR3_DQS 72 73 FB_C_WDQS3 GDDR3_40SE GDDR3_DQS 72 73 FB_C_RDQS0 GDDR3_40SE GDDR3_DQS 72 73 FB_C_RDQS1 GDDR3_40SE GDDR3_DQS 72 73 FB_C_RDQS2 GDDR3_40SE GDDR3_DQS 72 73 FB_C_RDQS3 GDDR3_40SE GDDR3_DQS 72 73 FB_C_DQ_BYTE0 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQ_BYTE1 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQ_BYTE2 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQ_BYTE3 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQM0 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQM1 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQM2 GDDR3_40SE GDDR3_DATA 72 73 FB_C_DQM3 GDDR3_40SE GDDR3_DATA 72 73 FB_D_WDQS0 GDDR3_40SE GDDR3_DQS 72 73 FB_D_WDQS1 GDDR3_40SE GDDR3_DQS 72 73 FB_D_WDQS2 GDDR3_40SE GDDR3_DQS 72 73 FB_D_WDQS3 GDDR3_40SE GDDR3_DQS 72 73 FB_D_RDQS0 GDDR3_40SE GDDR3_DQS 72 73 FB_D_RDQS1 GDDR3_40SE GDDR3_DQS 72 73 FB_D_RDQS2 GDDR3_40SE GDDR3_DQS 72 73 FB_D_RDQS3 GDDR3_40SE GDDR3_DQS 72 73 FB_D_DQ_BYTE0 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQ_BYTE1 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQ_BYTE2 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQ_BYTE3 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQM0 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQM1 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQM2 GDDR3_40SE GDDR3_DATA 72 73 FB_D_DQM3 GDDR3_40SE GDDR3_DATA 72 74 72 74 72 74 D 72 74 72 74 72 74 72 74 72 74 72 74 FB_B_LMA FB_B_UMA 72 74 72 74 FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS 72 74 72 74 72 74 72 74 FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS 72 74 72 74 72 74 72 74 FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ 72 74 72 74 72 74 72 74 FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 72 74 72 74 72 74 72 74 FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS C 72 74 72 74 72 74 72 74 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT ELECTRICAL_CONSTRAINT_SET www.laptop-schematics.com PHYSICAL_RULE_SET TABLE_SPACING_RULE_ITEM DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 MUXGFX Net Properties FB_B_DQ_BYTE1 GDDR3_40SE GDDR3_DATA FB_B_DQ_BYTE2 GDDR3_40SE GDDR3_DATA FB_B_DQ_BYTE3 GDDR3_40SE GDDR3_DATA FB_B_DQM0 GDDR3_40SE GDDR3_DATA FB_B_DQM1 GDDR3_40SE GDDR3_DATA FB_B_DQM2 GDDR3_40SE GDDR3_DATA FB_B_DQM3 GDDR3_40SE GDDR3_DATA FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS 72 74 72 74 72 74 72 74 FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ 72 74 72 74 72 74 72 74 FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 72 74 72 74 72 74 72 74 G96 Net Properties NET_TYPE NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET B I148 LVDS_A_CLK I149 LVDS_A_CLK LVDS_100D LVDS LVDS_100D LVDS I199 LVDS_A_DATA LVDS_100D LVDS I198 LVDS_A_DATA LVDS_100D LVDS I152 LVDS_B_CLK LVDS_100D LVDS I153 LVDS_B_CLK LVDS_100D LVDS I201 LVDS_B_DATA LVDS_100D LVDS I200 LVDS_B_DATA LVDS_100D LVDS LVDS_A_CLK_P LVDS_A_CLK_N LVDS_100D LVDS I182 LVDS_100D LVDS I184 LVDS_100D LVDS I185 LVDS_100D LVDS I190 LVDS_100D LVDS I191 LVDS_100D LVDS I192 LVDS_100D LVDS I193 LVDS_100D LVDS I194 LVDS_100D LVDS I195 LVDS_100D LVDS I196 LVDS_100D LVDS I197 LVDS_100D LVDS SPACING (CK505_DOT96) CLK_SLOW_55S CLK_SLOW CK505_CLK27MSS CLK_SLOW_55S CLK_SLOW LVDS_EG_A_CLK LVDS_100D LVDS LVDS_EG_A_CLK LVDS_100D LVDS LVDS_EG_A_DATA LVDS_100D LVDS LVDS_EG_A_DATA LVDS_100D LVDS 80 83 LVDS_EG_B_DATA LVDS_100D LVDS 80 83 LVDS_EG_B_DATA LVDS_100D LVDS DP_ML DP_ML DP_AUX_CH DP_AUX_CH DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D 80 83 LVDS_A_DATA_P LVDS_A_DATA_N 80 83 80 83 LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA_P LVDS_B_DATA_N 80 83 I142 80 83 I144 I183 PHYSICAL 80 83 LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N 79 I145 79 I143 79 I139 79 I138 DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT GPU_CLK27M GPU_CLK27M_SS LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N DP_EG_ML_P DP_EG_ML_N DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_AUX_CH_C_P DP_EG_AUX_CH_C_N 76 76 77 83 B 77 83 77 83 77 83 77 83 77 83 77 80 77 80 77 80 77 80 80 80 79 80 79 80 79 80 79 80 79 80 79 80 79 80 79 80 GPU (G96) Constraints A I161 DP_ML I160 I155 DP_ML I157 I202 DP_ML I203 DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_ML_C_P DP_ML_C_N DP_ML_P DP_ML_N DP_ML_CONN_P DP_ML_CONN_N SYNC_MASTER=MUXGFX 81 81 SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY 80 81 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 80 81 81 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 81 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I159 I158 DP_AUX_CH DP_AUX_CH DP_100D DP_100D DISPLAYPORT DISPLAYPORT DP_AUX_CH_C_P DP_AUX_CH_C_N SIZE 80 81 DRAWING NUMBER D 80 81 APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 94 96 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP M99 Specific Net Properties M99 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET PHYSICAL TABLE_PHYSICAL_RULE_ITEM THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR SPACING ENET_MDI_100D ENETCONN ENET_MDI_100D ENETCONN SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA SATA SATA SATA SATA SATA SATA SATA SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE ELECTRICAL_CONSTRAINT_SET ENETCONN_P ENETCONN_N =1:1_DIFFPAIR 35 I164 35 TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR I146 I145 I144 I142 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I143 TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? I140 I141 TABLE_SPACING_RULE_ITEM I139 TABLE_SPACING_RULE_ITEM AUDIO * ? =2:1_SPACING TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * 25 MILS THERM_1TO1_55S I125 TABLE_SPACING_RULE_ITEM ENETCONN CPUTHMSNS_D2_DP I124 WEIGHT ? CPU_THERMD_DP I127 I126 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING I130 TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V8_MEM * =STANDARD ? GPU_THERMD_DP I129 TABLE_SPACING_RULE_ITEM I138 SPACING_RULE_SET LAYER LINE-TO-LINE SPACING MCPTHMSNS_D_DP WEIGHT I135 MCP_THERMD_DP TABLE_SPACING_RULE_ITEM GND_P2MM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 I156 SENSE_DIFFPAIR I157 I155 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE I154 SPACING_RULE_SET I153 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * GND_P2MM GND * I151 GND_P2MM C GND * GND_P2MM MEM_DATA GND * GND_P2MM SENSE_DIFFPAIR I149 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM I148 I158 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM SENSE_DIFFPAIR I147 I186 THERM THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S I150 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL SENSE_DIFFPAIR I152 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD THERM THERM_1TO1_55S THERM_1TO1_55S I136 TABLE_SPACING_RULE_ITEM THERM_1TO1_55S THERM_1TO1_55S I137 TABLE_SPACING_RULE_HEAD THERM THERM_1TO1_55S GPUTHMSNS_D_DP I128 WEIGHT THERM THERM_1TO1_55S SENSE_DIFFPAIR I185 SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE (PCIE_EXCARD) (PCIE_EXCARD) I163 39 I161 39 (PCIE_MINI) (PCIE_MINI) NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_FSB GND * GND_P2MM CPU_COMP GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_PCIE GND * GND_P2MM CPU_GTLREF GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM PCIE GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE GND * GND * GND_P2MM I131 GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM SATA SB_POWER I132 TABLE_SPACING_ASSIGNMENT_ITEM FSB_DSTB FSB_DSTB * SENSE_DIFFPAIR GND_P2MM I134 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM USB GND * GND_P2MM CLK_PCIE SB_POWER * PWR_P2MM I133 SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE 32 89 31 89 31 89 USB USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB I174 USB_90D USB I172 USB_90D USB 39 I167 39 I165 78 I182 78 I181 47 65 I179 47 65 I180 48 I177 48 I178 10 48 I176 10 48 I175 (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTD) (USB_EXTD) (USB_CAMERA) (USB_CAMERA) I173 USB_90D USB I171 USB_90D USB I169 USB_90D USB I170 USB_90D I183 DP_100D DISPLAYPORT DP_100D DISPLAYPORT 48 USB 21 48 I187 MCP_PE4_REFCLK 47 I188 47 PCIE_FC_R2D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE I192 PCIE_90D PCIE I193 PCIE_90D PCIE I194 PCIE_90D PCIE I189 47 I190 47 I191 PCIE_FC_D2R 47 47 66 47 66 47 CLK_PCIE_100D CLK_PCIE_100D DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR I195 47 I196 47 I198 SPK_OUT 47 I197 46 I201 SPK_OUT 46 I199 SPK_OUT I207 I204 I205 I208 I203 46 61 40 40 40 40 31 31 31 31 40 40 USB2_EXCARD_CONN_P USB2_EXCARD_CONN_N 48 47 46 61 USB_LT2_P USB_LT2_N 48 76 CLK_PCIE CLK_PCIE AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO D 61 CONN_TPAD_USB_P CONN_TPAD_USB_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N CONN_USB2_BT_P CONN_USB2_BT_N 48 76 I184 31 61 USB2_LT1_P USB2_LT1_N 48 21 48 31 CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N 48 I206 SB_POWER PCIE USB I166 PP3V3_S5 PP3V3_S0 PP1V5_S0 P1V8GPUISNS_P P1V8GPUISNS_N P1V8GPUISNS_R_P P1V8GPUISNS_R_N SB_POWER TABLE_SPACING_ASSIGNMENT_ITEM PCIE PCIE_90D 32 89 USB_90D I168 39 I202 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_90D PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_MINI_R2D_P PCIE_MINI_R2D_N USB_90D I159 39 TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 PCIE PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N 39 GND GND PCIE PCIE_90D CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR I160 I200 TABLE_SPACING_ASSIGNMENT_HEAD SPACING PCIE_90D 39 1V05CPUISNS_R_P 1V05CPUISNS_R_N DDRISNS_R_P DDRISNS_R_N GPUISENS_P GPUISENS_N 1V05CPU_P 1V05CPU_N DDRISNS_P DDRISNS_N P1V8GPU_P P1V8GPU_N ISNS_CPU_P ISNS_CPU_N SENSE SENSE_1TO1_55S I162 SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N GFXIMVP6_VSEN_P GFXIMVP6_VSEN_N MCPCOREISNS_P MCPCOREISNS_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N MCPTHMSNS_D_P MCPTHMSNS_D_N MCP_THMDIODE_P MCP_THMDIODE_N PHYSICAL www.laptop-schematics.com SENSE_1TO1_55S 32 32 DP_IG_AUX_CH_C_P 80 DP_IG_AUX_CH_C_N 80 PCIE_CLK100M_FC_P 32 PCIE_CLK100M_FC_N 32 PCIE_FC_R2D_C_P 32 PCIE_FC_R2D_C_N 32 PCIE_FC_D2R_P 32 PCIE_FC_D2R_N 32 PCIE_FC_R2D_P 32 PCIE_FC_R2D_N 32 PCIE_CLK100M_EXCARD_CONN_N 32 PCIE_CLK100M_EXCARD_CONN_P 32 SPKRCONN_L_P_OUT 57 58 SPKRCONN_L_N_OUT 57 58 SPKRCONN_S_P_OUT 57 58 SPKRCONN_S_N_OUT 57 58 SPKRCONN_R_P_OUT 57 58 SPKRCONN_R_N_OUT 57 58 SPKRAMP_L_P_OUT 57 SPKRAMP_L_N_OUT 57 SPKRAMP_R_P_OUT 57 SPKRAMP_R_N_OUT 57 SPKRAMP_S_P_OUT 57 SPKRAMP_S_N_OUT 57 C 47 47 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA SB_POWER * ENET_MDI GND * GND_P2MM PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB SB_POWER * PWR_P2MM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.25 MM 250 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.23 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE TABLE_SPACING_ASSIGNMENT_HEAD B NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM LVDS GND * GND_P2MM MEM_40S_VDD * OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE B TABLE_PHYSICAL_RULE_ITEM MEM_70D * OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE 0.09 MM 500 MIL OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM Memory Constraint Relaxations MEM_70D_VDD * OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout PCIE_90D * OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_70D BOTTOM 0.127 MM 6.35 MM TABLE_PHYSICAL_RULE_ITEM USB_90D TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP * OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM Graphics ,SATA Constraint Relaxations CPU_27P4S BOTTOM OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) PHYSICAL_RULE_SET LAYER MEM_40S ISL4,ISL9 OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM A LVDS_100D BGA 100_DIFF_BGA DP_100D BGA 100_DIFF_BGA Project Specific Constraints SYNC_MASTER=MUXGFX TABLE_PHYSICAL_RULE_ITEM MEM_40S_VDD TABLE_PHYSICAL_ASSIGNMENT_ITEM OVERRIDE ISL3,ISL10 OVERRIDE N OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SYNC_DATE=02/21/2008 NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_ITEM MEM_70D TABLE_PHYSICAL_ASSIGNMENT_ITEM SATA_100D BGA 100_DIFF_BGA ISL4,ISL9 OVERRIDE OVERRIDE OVERRIDE MEM_70D_VDD ISL3,ISL10 OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_ITEM OVERRIDE N I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7546 A.0.0 OF 95 96 A M99 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 14 MM MM MM DEFAULT * 0.1 MM * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM FSB_DSTB FSB_DSTB BGA BGA_P3MM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT D TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P3MM * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TOP,BOTTOM Y * 0.15 MM ? 1.8:1_SPACING * 0.18 MM ? NOTE:From T18 MLB, changed to reflect M99 stackup TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE 1.5:1_SPACING DIFFPAIR NECK GAP 0.110 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.095 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD 2:1_SPACING * 0.2 MM ? TABLE_SPACING_RULE_ITEM 2X_DIELECTRIC * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? 5X_DIELECTRIC * 0.350 MM ? =STANDARD TABLE_SPACING_RULE_ITEM 2.5:1_SPACING * 0.25 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? www.laptop-schematics.com PHYSICAL_RULE_SET TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM 40_OHM_SE * Y 0.135 MM 0.135 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.095 MM 27P4_OHM_SE * Y 0.250 MM 0.250 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF ISL3,ISL4 Y 0.160 MM 0.160 MM 0.175 MM 0.175 MM 70_OHM_DIFF ISL9,ISL10 Y 0.160 MM 0.160 MM 0.175 MM 0.175 MM 70_OHM_DIFF ISL2,ISL11 Y 0.170 MM 0.170 MM 0.150 MM 0.150 MM 70_OHM_DIFF TOP,BOTTOM Y 0.170 MM 0.095 MM 0.150 MM 0.150 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4 Y 0.125 MM 0.125 MM 0.180 MM 0.180 MM 80_OHM_DIFF ISL9,ISL10 Y 0.125 MM 0.125 MM 0.180 MM 0.180 MM 80_OHM_DIFF ISL2,ISL11 Y 0.140 MM 0.140 MM 0.190 MM 0.190 MM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.095 MM 0.190 MM 0.190 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL2,ISL11 Y 0.115 MM 0.115 MM 0.230 MM 0.230 MM 90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.095 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF A ISL9,ISL10 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM PCB Rule Definitions TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=M99_MLB TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL2,ISL11 Y 0.089 MM 0.089 MM 0.220 MM NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers 0.220 MM 100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.220 MM SYNC_DATE=01/22/2008 NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_ITEM 0.220 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF ISL3,ISL4 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL9,ISL10 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL2,ISL11 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM SIZE TABLE_PHYSICAL_RULE_ITEM APPLE INC TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM 0.330 MM DRAWING NUMBER D TABLE_PHYSICAL_RULE_ITEM SCALE SHT 0.330 MM NONE REV 051-7546 A.0.0 OF 96 96 A ... (PAGE 43) D6905 D www .laptop- schematics.com A.0.0 OF 96 A D C C B B www .laptop- schematics.com D Power Block Diagram SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION... SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN M98_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM www .laptop- schematics.com TABLE_BOMGROUP_ITEM... System Block Diagram U6600,6605,6610,6620 SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER,