5 Project code: 91.4BW01.001 PCB P/N : 48.4BW01.0SB REVISION : 08242-SB HM40-MV Block Diagram CLK GEN D ICS 9LPRS365BKLFT (71.09365.A03) SILEGO SLG8SP513VTR(71.08513.003) Mobile CPU PCB STACKUP THERMAL EMC2102 Penryn 479 32 TOP VCC 4, DDR2 DIMM1 667/800 MHz HOST BUS 667/800MHz 667/800 MHz Cantiga SYSTEM DC/DC TPS51125 GND CRT AGTL+ CPU I/F INPUTS 667/800MHz BOTTOM 19 5V_S5 INTEGRATED GRAHPICS DCBATOUT LCD LVDS, CRT I/F 3D3V_S5 18 6,7,8,9,10,11 17 X4 DMI 400MHz Codec AZALIA CX20561 SYSTEM DC/DC C-Link0 TPS51124 INPUTS ICH9M PCIex1 PCIe ports OUTPUTS SATA DCBATOUT LAN TXFM Atheros AR8114 AR8132 ACPI 2.0 MIC In 25 24 1D8V_S3 RJ45 25 RT9026 43 DDR_VREF_S0 1D8V_S3 DDR_VREF_S3 12 USB 2.0/1.1 ports 28 ETHERNET (10/100/1000MbE) PCIex1 High Definition Audio OP AMP CPU DC/DC LPC BUS ISL6266A 28 BIOS KBC Winbond W25X16 16M Bits KBC773L 33 12,13,14,15 INPUTS LPC 34 Blue Tooth 22 (USB) ODD SATA A INT KB 33 INPUTS DCBATOUT USB Port 23 0.35~1.5V CardReader Realtek RTS5159 30 46 OUTPUTS BT+ 20 SATA VCC_CORE_S0 BQ24745 Touch Pad 35 SATA 21 MS/MS Pro/xD 30 /MMC/SD DCBATOUT UMA Two Phase A in Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Power Board Title 36 Size A3 Date: B CHARGER Camera (USB) 18 USB 41 OUTPUTS DCBATOUT DEBUG CONN.34 USB HDD SATA 1D5V_S0 31 Active Managemnet Technology(DO) Line Out (NO SPDIF) 43 1D8V_S3 a/b/g/n Serial Peripheral I/F Matrix Storage Technology(DO) INT.SPKR RT9018A Mini Card Kedron LPC I/F G1454 27 C 44 1D05V_S0 PCI/PCI BRIDGE 26 28 42 OUTPUTS DDR Memory I/F C B S 667/800/1067MHz@1.05V S 16 DDR2 DIMM2 D BLOCK DIAGRAM Document Number Rev SB HM40-MV Monday, November 24, 2008 Sheet 1 of 51 A B C ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5 D ICH9M Integrated Pull-up and Pull-down Resistors page 92 Comment Signal Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) This signal has weak internal pull-down CL_CLK[1:0] CL_DATA[1:0] PULL-UP 20K HDA_SYNC PCIE config1 bit0, Rising Edge of PWROK This signal has a weak internal pull-down Sets bit0 of RPC.PC(Config Registers:Offset 224h) CL_RST0# PULL-UP 20K GNT2#/ GPIO53 PCIE config2 bit2, Rising Edge of PWROK DPRSLPVR/GPIO16 PULL-DOWN 20K ENERGY_DETECT PULL-UP 20K GPIO20 Reserved This signal has a weak internal pull-up Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high HDA_BIT_CLK PULL-DOWN 20K GNT1#/ GPIO51 ESI Strap (Server Only) Rising Edge of PWROK HDA_DOCK_EN#/GPIO33 PULL-UP 20K HDA_RST# PULL-DOWN 20K HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K GNT3#/ GPIO55 GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI GPIO49 Top-Block Swap Override Rising Edge of PWROK ICH9 EDS 642879 SIGNAL ESI compatible mode is for server platforms only This signal should not be pulled low for desttop and mobile Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space) Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down CFG[2:0] CFG[4:3] CFG8 CFG[15:14] CFG[18:17] Strap Description Boot BIOS Destination Selection 0:1 Rising Edge of PWROK Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10) GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K GPIO[20] PULL-DOWN 20K Integrated TPM Enable, Rising Edge of CLPWROK Sample low: the Integrated TPM will be disabled Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable GPIO[49] PULL-UP 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K PWRBTN# PULL-UP 20K SATALED# PULL-UP 15K No Reboot Rising Edge of PWROK If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature) The status is readable via the NO REBOOT bit SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K SPI_MOSI PULL-DOWN 20K SPI_MISO PULL-UP 20K TP3 XOR Chain Entrance Rising Edge of PWROK This signal should not be pull low unless using XOR Chain testing SPKR PULL-DOWN 20K TACH_[3:0] PULL-UP 20K GPIO33/ HDA_DOCK _EN# Flash Descriptor Security Override Strap Rising Edge of PWROK Sampled low:the Flash Descriptor Security will be overridden If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister TP[3] PULL-UP 20K USB[11:0][P,N] PULL-DOWN 15K 0.5 Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved FSB Frequency Select Reserved CFG5 DMI x2 Select CFG6 iTPM Host Interface = DMI x2 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) = Transport Layer Security (TLS) cipher suite with no confidentiality = TLS cipher suite with confidentiality (default) CFG7 Intel Management engine Crypto strap CFG9 PCIE Graphics Lane = Reverse Lanes,15->0,14->1 ect 1= Normal operation(Default):Lane Numbered in order CFG10 PCIE Loopback enable = Enable (Note 3) 1= Disabled (default) PULL-DOWN 20K Signal has weak internal pull-up Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) SPKR Pin Name The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller PCI Express Lane Reversal Rising Edge of PWROK SATALED# page 218 PULL-UP 20K GLAN_DOCK# DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK applications and required to be high for mobile applications Montevina Platform Design guide 22339 Rev.1.5 Resistor Type/Value HDA_SYNC E Cantiga chipset and ICH9M I/O controller Hub strapping configuration CFG[13:12] CFG16 CFG19 00 10 01 11 XOR/ALL = = = = Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default) FSB Dynamic ODT = Dynamic ODT Disabled = Dynamic ODT Enabled (Default) DMI Lane Reversal = Normal operation(Default): Lane Numbered in Order = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) CFG20 SDVO_CTRLDATA Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe = Only Digital Display Port or PCIE is operational (Default) =Digital display Port and PCIe are operting simulataneously via the PEG port =No SDVO Card Present (Default) SDVO Present = SDVO Card Present L_DDC_DATA Local Flat Panel (LFP) Present = LFP Disabled (Default) 1= LFP Card Present; PCIE disabled NOTE: All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware This 'Soft-Strap' is activated only after enabling iTPM via CFG6 Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time 2 SMBus EMC2102 Thermal USB Table USB PCIE Routing LANE1 LAN Atheros AR8114A LANE2 MiniCard WLAN LANE3 NC LANE4 NC LANE5 NC LANE6 NC Pair KBC BAT_SCL Device USB1 NC NC MINIC1 WEBCAM NC NC Bluetooth NC USB2(High speed) 10 NC 11 CardReader BATTERY UMA Two Phase ICH9M Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title SMBC_ICH 9LPRS365BKLFT DDR Size A3 Date: Reference Document Number Rev SB HM40-MV Monday, November 24, 2008 Sheet of 51 C D GEN_XTAL_OUT 2 DY DY 1 EC33 DY EC34 EC66 EC62 DY 19 27 43 52 33 56 DY 1 EC31 CLK48_5159 X1 X2 61 60 CLK_CPU_BCLK CLK_CPU_BCLK# CPU CPUT1_F CPUC1_F 58 57 CLK_MCH_BCLK CLK_MCH_BCLK# NB CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 54 53 CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24 LAN EC25 CPUT0 CPUC0 PCLK_FW H DY 82.30005.891 2nd = 82.30005.951 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO 16 46 62 23 VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 R91 0R2J-2-GP CLK48_ICH Do Not Stuff X4 X-14D31818M-35GP U14 1126 modify RN61 and RN62 Do Not Stuff C229 SB SC33P50V2JN-3GP GEN_XTAL_IN PCLK_ICH Do Not Stuff RN61 and RN62 SB 1120 modify RN61 and RN62 CL=20pF±0.2pF PCLK_KBC Do Not Stuff SB 1120 add RN61 and RN62 3D3V_CLKPLL_S0 Do Not Stuff SB 1127 swap the nets of SRN470J-3-GP 2 1 2 1 1 2 CLK_ICH14 3D3V_48MPW R_S0 Do Not Stuff PCIE_REQ_LAN#_R PCLKCLK0 PCIE_REQ_MINI#_R PCLKCLK1 C205 DY 0915 add EC34 for EMI demand RN62 24 PCIE_REQ_LAN# 13 SATACLKREQ# 31 PCIE_REQ_MINI# CLK_MCH_OE# Do Not Stuff 3D3V_CLKGEN_S0 R87 C1550R2J-2-GP SCD1U16V2ZY-2GP DY C224 SCD1U16V2ZY-2GP C152 C226 SCD1U16V2ZY-2GP DY 3D3V_CLKGEN_S0 C179 SCD1U16V2ZY-2GP 0R2J-2-GP DY C204 Do Not Stuff C173 Do Not Stuff C196 DY Do Not Stuff C156 Do Not Stuff R80 SCD1U16V2ZY-2GP C176 SCD1U16V2ZY-2GP C149 SC4D7U10V5ZY-3GP DY SRN10KJ-6-GP RN61 C165 3D3V_S0 1015 modify component size of R87 1015 modify component size of R80 3D3V_CLKPLL_S0 Do Not Stuff Do Not Stuff DY 3D3V_S0 C227 SC1U16V3ZY-GP C221 3D3V_48MPW R_S0 0R2J-2-GP R95 DY R302 Do Not Stuff SB 1124 add R302 1015 modify component size of R95 3D3V_S0 E 3D3V_S0 1D05V_S0 B A RN20 GEN_XTAL_OUT_R 30 13 C230 SC33P50V2JN-3GP CLK48_5159 CLK48_ICH 4,7 CPU_SEL0 R88 CLK48 17 USB_48MHZ/FSLA SRN22-3-GP 2K2R2J-2-GP 13 PM_STPPCI# 13 PM_STPCPU# 45 44 15,16,17 SMBC_ICH 15,16,17 SMBD_ICH 13 CLK_PW RGD Do Not Stuff 63 SRCT7/CR#_F SRCC7/CR#_E 51 50 SRCT6 SRCC6 48 47 SRCT10 SRCC10 41 42 SRCT11/CR#_H SRCC11/CR#_G 40 39 SRCT9 SRCC9 37 38 CLK_PCIE_MINI1 31 CLK_PCIE_MINI1# 31 SRCT4 SRCC4 34 35 CLK_MCH_3GPLL CLK_MCH_3GPLL# SRCT3/CR#_C SRCC3/CR#_D 31 32 SRCT2/SATAT SRCC2/SATAC 28 29 CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 24 25 DREFSSCLK DREFSSCLK# SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 DREFCLK DREFCLK# PCI_STOP# CPU_STOP# 3D3V_S0 CPU_SEL2 3D3V_S0 4,7 R89 RN28 SRN10KJ-6-GP DY PCLKCLK0 PCLKCLK1 PCLKCLK2 RN23 PCLKCLK2 CPU_SEL2_R PCLKCLK4 PCLKCLK5 13 CLK_ICH14 33 13 PCLK_KBC PCLK_ICH 4,7 CPU_SEL1 CPU_SEL2_R PCLKCLK3 PCLKCLK4 PCLKCLK5 SCLK SDATA CK_PWRGD/PD# 10 11 12 13 14 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN 64 FSLB/TEST_MODE REF0/FSLC/TEST_SEL SRN33J-7-GP NC#55 ICS9LPRS365BKLFT-GP-U ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION 71.09365.A03 2nd = 71.08513.003 PCI0/CR#_A Byte 5, bit = PCI0 enabled (default) 1= CR#_A enabled Byte 5, bit controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PCI1/CR#_B Byte 5, bit = PCI1 enabled (default) 1= CR#_B enabled Byte 5, bit controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair PCI2/TME = Overclocking of CPU and SRC Allowed = Overclocking of CPU and SRC NOT allowed PCI3 3.3V PCI clock output PCI4/27M_SEL = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96# = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0# PCI_F5/ITP_EN =SRC8/SRC8# = ITP/ITP# SRCT3/CR#_C Byte 5, bit = SRC3 enabled (default) 1= CR#_C enabled Byte 5, bit controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair GND 1014 add ER5 for EMI deamnd B SB 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#) SB PCIE_REQ_MINI#_R 1126 add the net(PCIE_REQ_MINI#) MINI1 NB CLK SB 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#) SB SATA NB CLK NB CLK (96 MHz) SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME DESCRIPTION SRCC3/CR#_D Byte 5, bit = SRC3 enabled (default) 1= CR#_D enabled Byte 5, bit controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair SRCC7/CR#_E Byte 6, bit = SRC7# enabled (default) 1= CR#_F controls SRC6 SRCT7/CR#_F Byte 6, bit = SRC7 enabled (default) 1= CR#_F controls SRC8 SRCC11/CR#_G Byte 6, bit = SRC11# enabled (default) 1= CR#_G controls SRC9 SRCT11/CR#_H Byte 6, bit = SRC11 enabled (default) 1= CR#_H controls SRC10 0 0 0 1 1 0 CPU FSB 100M 133M 166M 200M 266M X 533M 667M 800M 1066M UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Clock Generator Document Number Rev HM40-MV Date: A SB DMI CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13 65 DY 55 GND GNDSRC GNDSRC GNDSRC GNDCPU GND PCLKCLK3 Do Not Stuff 22 30 36 49 59 26 ER5 GND48 GNDPCI GNDREF PCLK_FW H 18 15 34 CPU_SEL2_R SB 1126 add the net(PCIE_REQ_LAN#) PCIE_REQ_LAN#_R C D Monday, December 01, 2008 Sheet E SB of 51 A B C D E H_A#[35 3] H_A#[35 3] H_DINV#[3 0] U33A OF H_TRDY# H_HIT# H_HITM# 6 H_THERMDA DY H_THERMDC XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# 1D05V_S0 R63 68R2-GP RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 BCLK0 BCLK1 B1 H_DSTBN#0 H_DSTBP#0 H_DINV#0 D21 CPU_PROCHOT# A24 B25 H_THERMDA 32 H_THERMDC 32 C7 PM_THRMTRIP-A# 7,12,39 A22 A21 R62 DY H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 CPU_PROCHOT#_R 41 Do Not Stuff CLK_CPU_BCLK CLK_CPU_BCLK# 1D05V_S0 PM_THRMTRIP# should connect to ICH9 and MCH without T-ing ( No stub) 6 R179 1KR2F-3-GP Layout Note: "CPU_GTLREF0" 0.5" max length H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_GTLREF0 HCLK 6 THERMTRIP# C438 Do Not Stuff PROCHOT# THRMDA THRMDC H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 R181 2KR2F-3-GP DY C352 Do Not Stuff KEY_NC BGA479-SKT6-GPU7 62.10079.001 Do Not Stuff Do Not Stuff 2nd: 62.10053.401 3,7 3,7 3,7 TP18 TP44 TP60 CPU_SEL0 CPU_SEL1 CPU_SEL2 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# AD26 TEST1 C23 TEST2 D25 1RSVD_CPU_12 C24 TEST4 AF26 1RSVD_CPU_13 AF1 1RSVD_CPU_14 A26 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 DATA GRP2 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 MISC BSEL0 BSEL1 BSEL2 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 R53 R51 R45 R44 1 54D9R2F-L1-GP XDP_TDI R48 54D9R2F-L1-GP XDP_BPM#5 R43 54D9R2F-L1-GP H_CPURST# R213 XDP_TCK R41 XDP_TRST# R42 1 DY 2 2 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSTP# 7,12,41 H_DPSLP# 12 H_DPW R# H_PW RGD 12,39,48 H_CPUSLP# PSI# 41 62.10079.001 Layout Note: Comp0, connect with Zo=27.4 ohm, make trace length shorter than 0.5" Comp1, connect with Zo=55 ohm, make trace length shorter than 0.5" Follow Demo Circuit R50 1 1 BGA479-SKT6-GPU7 1D05V_S0 XDP_TMS U33B OF DATA GRP3 BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# H_RS#0 H_RS#1 H_RS#2 G6 E4 H_D#[63 0] 12 HIT# HITM# CONTROL C1 F3 F4 G3 G2 H_INIT# H_LOCK# H_CPURST# 6,48 H_RS#[2 0] RSVD_CPU_11 RESET# RS0# RS1# RS2# TRDY# H_BREQ#0 TP20 H4 H_DSTBP#[3 0] H_IERR# Do Not Stuff Do Not Stuff LOCK# H_DSTBN#[3 0] Place testpoint on H_IERR# with a GND 0.1" away R64 56R2J-4-GP THERMAL ICH F1 D20 B3 H_D#[63 0] STPCLK# LINT0 LINT1 SMI# H_DEFER# H_DRDY# H_DBSY# H_DSTBP#[3 0] 1D05V_S0 H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 H5 F21 E1 6 A20M# FERR# IGNNE# H_ADS# H_BNR# H_BPRI# DATA GRP1 H_A20M# H_FERR# H_IGNNE# A6 A5 C4 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 BR0# TP11 Do Not Stuff H1 E2 G5 IERR# INIT# H_DINV#[3 0] H_DSTBN#[3 0] DATA GRP0 H_ADSTB#1 A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# ADDR GROUP 12 12 12 12 DEFER# DRDY# DBSY# REQ0# REQ1# REQ2# REQ3# REQ4# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 Side Band Non GTL 12 12 12 K3 H2 K2 J3 L1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 H_REQ#[4 0] A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# RESERVED 6 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 1 R65 DY TEST1 Do Not Stuff Do Not Stuff R215 DY 2 54D9R2F-L1-GP C343 Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals TEST2 Do Not Stuff TEST4 Do Not Stuff DY 54D9R2F-L1-GP UMA Two Phase 3D3V_S0 All place within 2" to CPU XDP_DBRESET# R60 DY Wistron Corporation Do Not Stuff 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 1D05V_S0 Title XDP_TDO R47 DY Do Not Stuff Size Document Number CPU (1 of 2) Rev SB HM40-MV Date: A B C D Monday, December 01, 2008 Sheet E of 51 A B C D E U33D VCC_CORE C79 C71 C49 2 C80 SC10U6D3V5MX-3GP C62 SC10U6D3V5MX-3GP C48 SC10U6D3V5MX-3GP C381 SC10U6D3V5MX-3GP TP46 NEC 77.E9071.011 SC10U6D3V5MX-3GP Do Not Stuff ST900U2D5VM-1-GP SC10U6D3V5MX-3GP TC6 1126 add C48,C49,C71,C79 SC10U6D3V5MX-3GP CAP C384 SC10U6D3V5MX-3GP CAP C382 Do Not Stuff CAP C383 Do Not Stuff CAP C61 Do Not Stuff C90 Do Not Stuff CAP Do Not Stuff CAP C70 C92 SB VCC_CORE DY 2 2 2 2 DY C52 Do Not Stuff DY C96 Do Not Stuff DY C93 Do Not Stuff DY C59 Do Not Stuff DY C53 Do Not Stuff DY C91 Do Not Stuff DY C97 Do Not Stuff 1D05V_S0 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA VCCA B26 C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCC_SENSE 41 VSSSENSE AE7 VSS_SENSE 41 1 2 2 2 2 C446 DY PBY160808T-121Y-GP 68.00206.021 2nd = 68.00230.041 BGA479-SKT6-GPU7 Layout Note: R39 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines should be of equal length 62.10079.001 Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line Do Not Stuff C66 SC4D7U6D3V3KX-GP C65 SCD1U10V2KX-4GP DY C63 Do Not Stuff R38 100R2F-L1-GP-U C83 SCD1U10V2KX-4GP DY C429 C82 SCD1U10V2KX-4GP VCC_CORE C420 SC10U6D3V5MX-3GP 41 Do Not Stuff H_VID[6 0] C81 SCD1U10V2KX-4GP L10 C69 SCD1U10V2KX-4GP 1D5V_S0 1D5V_VCCA_S0 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 C78 SCD1U10V2KX-4GP layout note: "1D5V_VCCA_S0" as short as possible C68 1 DY 1D05V_S0 C84 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C54 Do Not Stuff VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 Do Not Stuff A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 SCD1U10V2KX-4GP VCC_CORE VCC_CORE U33C OF Do Not Stuff VCC_CORE VCC_CORE A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 OF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 Do Not Stuff TP45 1 Do Not Stuff Do Not Stuff TP48 TP21 1 Do Not Stuff Do Not Stuff TP61 TP43 BGA479-SKT6-GPU7 62.10079.001 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Document Number CPU (2 of 2) Rev SB HM40-MV Date: A B C D Monday, December 01, 2008 Sheet E of 51 1 OF 10 U35A H_A#[35 3] H_SWING routing Trace width and Spacing use 10 / 20 mil H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1D05V_S0 D H_D#[63 0] H_D#[63 0] R239 221R2F-2-GP H_SWING Resistors and Capacitors close MCH 500 mil ( MAX ) 1 H_SW ING R238 100R2F-L1-GP-U 2 C478 SCD1U10V2KX-4GP C H_RCOMP routing Trace width and Spacing use 10 / 20 mil R226 24D9R2F-L-GP H_RCOMP Place them near to the chip ( < 0.5") B F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST H_SW ING H_RCOMP 4,48 H_CPURST# H_CPUSLP# H_AVREF A11 B11 R240 2KR2F-3-GP C12 E11 C479 SCD1U16V2ZY-2GP H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_RS#_0 H_RS#_1 H_RS#_2 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 H_AVREF H_DVREF D H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPW R# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DSTBN#[3 0] H_DSTBP#[3 0] H_REQ#[4 0] H_RS#[2 0] C H_DINV#[3 0] H_DSTBN#[3 0] H_DSTBP#[3 0] H_REQ#[4 0] H_RS#[2 0] B 4 CANTIGA-GM-GP-U-NF 1 R241 1KR2F-3-GP C5 E3 A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H_DINV#[3 0] 1D05V_S0 H_A#[35 3] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 71.CNTIG.00U UMA Two Phase A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Cantiga (1 of 6)_HOST Document Number Rev SB HM40-MV Date: W ednesday, November 26, 2008 Sheet of 51 2 OF 10 U35B DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# CLK R247 80D6R2F-L-GP M_RCOMPP PEG_CLK PEG_CLK# 100R2J-2-GP C147 DY Do Not Stuff B RN29 PM_EXTTS#0 PM_EXTTS#1 SRN10KJ-5-GP BG22 BH21 M_RCOMPP M_RCOMPN BF28 BH28 SM_RCOMP_VOH SM_RCOMP_VOL AV42 AR36 BF17 BC36 SM_REXT 1R243 TP_SM_DRAMRST# B38 A38 E41 F41 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# 18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2- H47 E46 G40 A40 18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+ H48 D45 F40 B40 DDR_VREF_S3 499R2F-2-GP TP36Do Not Stuff DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 A41 H38 G37 J37 0912 delete GMCH_TXB* C250 DMI AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 B42 G38 F37 K37 TVA_DAC TVB_DAC TVC_DAC 13 13 13 13 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 F25 H25 K25 TVA_DAC TVB_DAC TVC_DAC CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF TV_DCONSEL_0 TV_DCONSEL_1 DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 19 13 13 13 13 GMCH_BLUE 19 GMCH_GREEN 19 DMI_RXP0 13 DMI_RXP1 13 DMI_RXP2 13 DMI_RXP3 13 GMCH_RED GMCH_BLUE E28 GMCH_GREEN G28 GMCH_RED 19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC 19 GMCH_VSYNC GMCH_DDCDATA GMCH_HS GMCH_VS DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC 49D9R2F-GP Close to GMCH as 500 mils D H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 C J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 CANTIGA-GM-GP-U-NF CL_CLK0 13 CL_DATA0 13 PWROK 13,39 CL_RST#0 13 CLPWROK_MCH R111 Do Not Stuff MCH_CLVREF 0912 add these parts for EMI demand 1017 delete these parts(EC208~EC210) CRT_IREF routing Trace width use 20 mil R93 1KR2F-3-GP 1014 swap these nets RN14 Do Not Stuff TP34 CLK_MCH_OE# MCH_ICH_SYNC# 13 MCH_TSATN# GMCH_BLUE R92 511R2F-2-GP GMCH_GREEN GMCH_RED B SRN150F-1-GP FOR Cantiga:500 ohm Teenah: 392 ohm 1D05V_S0 RN15 56R2J-4-GP HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PEG_CMP 71.CNTIG.00U 1D05V_S0 B12 T37 T36 FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm R242 TSATN# PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 CRT_RED H32 J32 J29 E29 L29 RN21 SRN33J-5-GP-U CRT_IREF R253 1K02R2F-1-GP C34 N28 M28 G36 E36 K36 H36 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 CRT_GREEN J28 GMCH_DDCCLK PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 CRT_BLUE G29 B33 B32 G33 F33 E33 AH37 AH36 AN36 AJ35 AH34 TV_RTN C31 E32 C231 NC 3D3V_S0 NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47 17 17 16 16 SCD1U10V2KX-4GP 4,12,39 PM_THRMTRIP-A# 13,41 PM_DPRSLPVR BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 M_ODT0 M_ODT1 M_ODT2 M_ODT3 L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK 1 R211 GFX_VR_EN ME PLT_RST1# Do Not Stuff GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 13,24,30,31,33,34 R110 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 MISC 13,39 PWROK R29 B7 N33 P32 AT40 AT11 T20 R32 PM PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PWROK_GD RSTIN# PM_THRMTRIP-A# PM_DPRSLPVR 13 PM_SYNC# 4,12,41 H_DPRSTP# BD17 AY17 BF15 AY13 M29 C44 B43 E37 E38 C41 C40 B37 A37 18 GMCH_TXACLK18 GMCH_TXACLK+ 2 Do Not Stuff DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 GRAPHICS VID DY DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 HDA CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 17 17 16 16 GMCH_LCDVDD_ON LIBG L_LVBG Do Not Stuff PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 VGA R98 T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 CFG20 T28 CFG 3D3V_S0 CPU_SEL0 CPU_SEL1 CPU_SEL2 M_CS0# M_CS1# M_CS2# M_CS3# TP73 TV C 3,4 3,4 3,4 BA17 AY16 AV16 AR13 18 GMCH_LCDVDD_ON PEG_COMPI PEG_COMPO L_CTRL_DATA L_DDC_CLK L_DDC_DATA H24 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 M_RCOMPN R246 80D6R2F-L-GP 17 17 16 16 M33 K33 J33 R99 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK GRAPHICS SM_VREF SM_PWROK SM_REXT SM_DRAMRST# M_CKE0 M_CKE1 M_CKE2 M_CKE3 LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID 18 CLK_DDC_EDID 18 DAT_DDC_EDID SCD1U10V2KX-4GP 1D8V_S3 SM_RCOMP_VOH SM_RCOMP_VOL BC28 AY28 AY36 BB36 L32 G32 M32 PCI-EXPRESS layout take note SM_RCOMP SM_RCOMP# 17 17 16 16 RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 2 BG23 BF23 BH18 BF18 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 AR24 AR21 AU24 AV20 L_BKLTCTL GMCH_BL_ON LCTLA_CLK 18 L_BKLTCTL 33 GMCH_BL_ON RESERVED#AY21 1 AY21 C483 C484 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 17 17 16 16 LVDS SM_RCOMP_VOL R248 1KR2F-3-GP SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 RESERVED#B31 RESERVED#B2 RESERVED#M1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 AP24 AT21 AV24 AU20 2 B31 B2 M1 SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 1 C487 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP R250 3K01R2F-3-GP C489 RSVD D SM_RCOMP_VOH DDR CLK/ CONTROL/COMPENSATION R251 1KR2F-3-GP RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24 1D05V_S0 OF 10 U35C M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 1D8V_S3 TVA_DAC TVB_DAC TVC_DAC B28 B30 B29 C29 A28 SRN75J-1-GP CANTIGA-GM-GP-U-NF 3D3V_S0 71.CNTIG.00U RN32 LCTLB_DATA LCTLA_CLK CLK_MCH_OE# SRN10KJ-6-GP RN22 Pin Name Strap Description Configuration GMCH_LCDVDD_ON GMCH_BL_ON Low = Only digital DisplayPort (SDVO/DP/HDMI) or PCIE is operational (default) LIBG A CFG20 Digital DisplayPort (SDVO/DP/HDMI) Concurrent with PCIE A SRN100KJ-8-GP-U R103 2K37R2F-GP Wistron Corporation High = Digital DisplayPort (SDVO/DP/HDMI) and PCIE are operating simultaneously via the PEG port 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (2 of 6)_DMI/PM/CFG Size Document Number Rev HM40-MV Date: SB Sheet Monday, December 01, 2008 of 51 B SA_RAS# SA_CAS# SA_WE# BB20 BD20 AY20 M_A_RAS# 17 M_A_CAS# 17 M_A_W E# 17 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_DQS[7 0] M_A_DQS#[7 0] M_A_A[14 0] M_A_DM[7 0] 17 M_A_DQS[7 0] 17 M_A_DQS#[7 0] 17 M_A_A[14 0] 17 M_B_DQ[63 0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 OF 10 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 M_B_BS#0 16 M_B_BS#1 16 M_B_BS#2 16 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 M_B_RAS# 16 M_B_CAS# 16 M_B_W E# 16 D M_B_DM[7 0] B M_A_BS#0 17 M_A_BS#1 17 M_A_BS#2 17 MEMORY BD21 BG18 AT25 SYSTEM A U35E 16 M_B_DQ[63 0] SA_BS_0 SA_BS_1 SA_BS_2 M_A_DM[7 0] MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 DDR D M_A_DQ[63 0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 OF 10 U35D 17 M_A_DQ[63 0] DDR CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF 71.CNTIG.00U 71.CNTIG.00U SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_DM[7 0] 16 M_B_DQS[7 0] M_B_DQS[7 0] 16 M_B_DQS#[7 0] M_B_DQS#[7 0] 16 M_B_A[14 0] C M_B_A[14 0] 16 B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Cantiga (3 of 6)_DDR Document Number Rev SB HM40-MV Date: W ednesday, November 26, 2008 Sheet of 51 G9 VCC_GMCH_35 T32 VCC CORE 2 C450 DY 2 C456 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC D POWER 1 2 2 2 1 2 1 VCC Do Not Stuff Place CAP where LVDS and DDR2 taps 1 2 1 2 2 C211 AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF C CANTIGA-GM-GP-U-NF SB 1118 delete TC27 1 C235 C253 C246 1 C172 2 C136 SCD22U10V2KX-1GP 2 C140 SC1U10V3KX-3GP C153 71.CNTIG.00U SC1U10V3KX-3GP VCC SM LF VCC GFX DY SC10U6D3V5MX-3GP C210 Do Not Stuff C208 SC10U6D3V5MX-3GP C202 DY Do Not Stuff SCD1U10V2KX-4GP C225 Place on the Edge AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH SCD47U16V3ZY-3GP CANTIGA-GM-GP-U-NF C203 SCD1U10V2KX-4GP C207 DY 1 1D8V_S3 VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF 1D05V_S0 VCC NCTF POWER Coupling CAP Do Not Stuff VCC GFX NCTF AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 Coupling CAP 370 mils from the Edge Do Not Stuff VCC SM DY SCD1U10V2KX-4GP Do Not Stuff Do Not Stuff Do Not Stuff DY C145 C177 SCD1U10V2KX-4GP C193 SCD1U10V2KX-4GP C175 SC1U10V3ZY-6GP SCD1U10V2KX-4GP C194 C144 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC FOR VCC SM VCC_AXG_SENSE VSS_AXG_SENSE 71.CNTIG.00U C164 DY DY C111 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 Coupling CAP SCD22U10V2KX-1GP AJ14 AH14 C183 C112 DY SCD1U10V2KX-4GP 1 C162 Place on the Edge SCD1U10V2KX-4GP Do Not Stuff Do Not Stuff C163 DY Do Not Stuff C VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG DY TC21 Do Not Stuff Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 DY 1D05V_S0 Do Not Stuff OF 10 U35F C455 SC10U6D3V5MX-3GP 1D05V_S0 1D05V_S0 SC10U6D3V5MX-3GP VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF Do Not Stuff BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 Do Not Stuff D TP33 TP32 U35G AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 667MTS 2400mA 800MTS 3000mA B 1D05V_S0 OF 10 1D8V_S3 B place near Cantiga A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Cantiga (4 of 6)_POWER Document Number Rev SB HM40-MV Date: Sheet Monday, December 01, 2008 of 51 1120 modify EC78 VTT 1 2 2 2 CRT A PEG 1 A SM 1D8V_SUS_SM_CK_RC V48 U48 V47 U47 U46 VCC_DMI VCC_DMI VCC_DMI VCC_DMI AH48 AF48 AH47 AG47 3D3V_HV_S0 106mA R104 Do Not Stuff VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_HV VCC_HV VCC_HV C35 B35 A35 C262 SC1KP50V2KX-1GP K47 C159 SC10U6D3V5MX-3GP 1D8V_S3 AXF SM CK VCC_TX_LVDS B C254 SC1U10V3KX-3GP VTTLF VTTLF VTTLF A8 L1 AB2 71.CNTIG.00U C133 1 2 C139 SCD1U10V2KX-4GP C244 SC10U6D3V5MX-3GP C198 2 DY VTTLF1 VTTLF2 VTTLF3 C467 SCD47U6D3V2KX-GP C218 DY C460 Do Not Stuff DY 1D05V_S0 456mA C457 C462 SC10U6D3V5MX-3GP VCCD_LVDS VCCD_LVDS C222 1 C466 DY HDA VCCD_PEG_PLL 1782mA M38 L37 1R2F-GP 1D8V_TXLVDS_S3 VCCD_HPLL R81 Do Not Stuff 119mA HV VCCD_QDAC 1D8V_S3 R82 C166 SCD1U10V2KX-4GP BF21 BH20 BG20 BF20 PEG L28 VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK 60.3mA C 124mA B22 B21 A21 CANTIGA-GM-GP-U-NF 1D8V_S3 VCCD_TVDAC AF1 VCC_AXF VCC_AXF VCC_AXF 2 DY 1D05V_S0 LVDS 1 C261 SCD1U10V2KX-4GP C239 C480 Do Not Stuff SC10U6D3V5MX-3GP VCC_HDA 1D05V_RUN_PEGPLL AA47 C201 SCD1U10V2KX-4GP R255 10R2F-L-GP SCD47U6D3V2KX-GP 2nd = 68.00214.051 C481 SCD47U6D3V2KX-GP A A32 M25 3D3V_HV_S0 R254 Do Not Stuff C497 BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81 Do Not Stuff 1D5VRUN_QDAC 1D05V_HV_S0 Do Not Stuff L4 3D3V_S0 SC22U6D3V5MX-2GP C134 SCD1U10V2KX-4GP 1D5V_S0 D D18 Do Not Stuff 35mA SCD1U10V2KX-4GP 1D5VRUN_QDAC 157.2mA 180ohm 100MHz VCCA_TV_DAC VCCA_TV_DAC 1D5V_S0 1D05V_S0 PBY160808T-181Y-GP B24 A24 50mA C181 68.00206.041 VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF DY POWER VTTLF C482 SCD01U16V2KX-3GP C260 SCD1U10V2KX-4GP 2nd = 68.00217.521 220ohm 100MHz AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 C138 Do Not Stuff DY 1D05V_S0 D TV/CRT 79mA 50mA 68.00119.111 VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM C135 1D05V_S0 C468 SCD1U10V2KX-4GP 1D05V_RUN_PEGPLL SBK160808T-221Y-N-GP AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 C214 322mA TV DY 1D05V_S0 VCCA_PEG_PLL C213 1D8V_SUS_SM_CK 3D3V_S0_DAC L5 VCCA_PEG_BG C220 C180 C184 M_VCCA_MPLL 1 2 DY 139.2mA 2 2nd = 68.00217.161 120ohm 100MHz Do Not Stuff 68.00119.101 C463 DY C178 DY SCD1U10V2KX-4GP VSSA_LVDS 26mA Do Not Stuff L13 C469 Do Not Stuff Do Not Stuff SC4D7U6D3V3KX-GP C464 1 1D05V_S0 C160 2 1 C157 M_VCCA_HPLL 68.00119.101 VCCA_LVDS C209 SC1U10V3KX-3GP C161 DY SC1U10V3KX-3GP 24mA 1D05V_RUN_PEGPLL AA48 SC1U10V3KX-3GP C169 2nd = 68.00217.161 B J48 C256 SCD1U10V2KX-4GP 720mA 2 1D05V_S0 DY SBK160808T-121Y-N-GP VCCA_MPLL DMI 2 C265 Do Not Stuff L12 AE1 AD48 M_VCCA_DPLLB 120ohm 100MHz SBK160808T-121Y-N-GP M_VCCA_MPLL 1D5V_S0 1D05V_S0 VCCA_HPLL 13.2mAJ47 Do Not Stuff C AD1 1D8V_TXLVDS_S3 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C267 VCCA_DPLLB M_VCCA_HPLL DY 65mA R116 Do Not Stuff C258 Do Not Stuff VCCA_DPLLA L48 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 SCD1U10V2KX-4GP SC10U6D3V5MX-3GP C263 F47 M_VCCA_DPLLB VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT 1D8V_TXLVDS_S3 M_VCCA_DPLLA Do Not Stuff M_VCCA_DPLLA PLL 2nd = 68.00084.A01 VCCA_DAC_BG VSSA_DAC_BG A LVDS 65mA C490 SCD1U10V2KX-4GP VCCA_CRT_DAC VCCA_CRT_DAC A CK 68.00331.011 1 HFB1608VF-102-GP 1113 modify 2nd of U19 1D05V_S0 R108 5mA B27 A26 M_VCCA_DAC_BG A25 B25 3D3V_S0_DAC R249 2 1 SB 2 SC4D7U10V3KX-GP C494 SCD1U10V2KX-4GP Do Not Stuff 74.09091.J3F 2nd = 74.09198.Q7FDY C492 SC4D7U6D3V3KX-GP EC78 EC77 Do Not Stuff G9091-330T11U-GP D 0R2J-2-GP C485 SC22U16V0KX-1GP SC2D2U6D3V3MX-1-GP 852mA OF 10 U35H SC4D7U6D3V3KX-GP NC#4 3D3V_CRTDAC_S0 SC4D7U6D3V3KX-GP VOUT 73mA SCD01U16V2KX-3GP VIN GND EN 1D05V_S0 R252 3D3V_S0_DAC 3D3V_S0_DAC U44 Imax = 300 mA 5V_S0 1015 modify component size of R252 SB A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Cantiga (5 of 6)_POWER Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 Sheet 10 of 51 TP_LEFT 1017 modify RN60 TP_L1 RN60 TP_LEFT#_1 TP_LEFT 35,48 TP_RIGHT 35,48 Cover Up Switch EC84 Do Not Stuff D 3D3V_AUX_S5 SRN470J-4-GP-U DY SW -TACT-119-GP 62.40009.671 TP_RIGHT VDD LID_CLOSE# OUT LID_CLOSE# 33 GND EC22 Do Not Stuff DY R40 Do Not Stuff DY U4 2nd = 62.40012.101 2 D 1 ME268-002-GP TP_RIGHT#_1 74.00268.07B EC21 SCD1U16V2ZY-2GP EC83 Do Not Stuff TP_R1 DY SW -TACT-119-GP 1016 modify U4 62.40009.671 C 1017 modify U4 2nd = 62.40012.101 C 1017 add U61,R52,EC24 and EC23 1020 delete U61,R52,EC24 and EC23 B B A A UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size SWITCHS Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 Sheet 37 of 51 1015 modify the power from 3D3V_S5 to 5V_S5 SB 1106 modify LED11 D D PW RLED#_FR 36 Q27 33 PW RLED R1 R2 DTC143ZUB-GP 84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K PW RLED#_FR STDBY_LED#_FR R291 604R2F-2-GP R292 100R2J-2-GP Blue PW RLED#_FR_R STDBY_LED#_FR_R LED11 SB Orange LED-BO-4-GP 83.00195.G70 2nd = 83.19223.A70 Q28 33 STDBY_LED R1 R2 DTC143ZUB-GP 84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K 1112 remove the signal( STDBY_LED#_FR) 1017 modify R291 and R293 1014 modify these LEDs(LED11,LED12) 1015 modify the power from 3D3V_S5 to 5V_S5 Blue 33 DC_BATFULL R1 604R2F-2-GP SB 1106 modify LED12 DC_BATFULL#_FR C 1106 modify LED power from 5V_S5 to 5V_AUX_S5 R2 DTC143ZUB-GP 84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K LED12 LED-BO-4-GP Q30 33 5V_AUX_S5 R293 Q29 C 5V_S5 CHARGE_LED R1 R294 100R2J-2-GP CHARGE_LED_FR Orange 83.00195.G70 2nd = 83.19223.A70 R2 DTC143ZUB-GP 84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K 1016 modify Q27~Q30 B B A A UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size LED Document Number Rev SB HM40-MV Date: W ednesday, November 26, 2008 Sheet 38 of 51 Aux Power 3D3V_AUX_S5 Run Power I = 300 mA 5V_AUX_S5 U43 3D3V_AUX_S5 DY C269 330KR2J-L1-GP DY R117 100KR2J-1-GP K R120 D9 PDZ9D1B-GP 3D3V_S0 3D3V_S5 83.9R103.C3F 2nd = 83.9R103.F3F U21 S S S G D D D D AO4468-GP 1016 modify D9 84.04468.037 Q12 Z_12V_D3 DY C278 Z_12V_D4 3D3V_runpwr 2 DY AO4468-GP A R115 Z_12V_G3 D D D D D S R118 U20 S S S G 84.04468.037 Z_12V 10KR2J-3-GP R109 Do Not Stuff 1113 modify 2nd of U43 D C372 Q11 Do Not Stuff G Z_12V_D3 S 2N7002DW -1-GP 84.27002.D3F PM_SLP_S3# 13,33,43,44 3D3V_S5 Do Not Stuff C257 U17 B A VCC Y DY PW ROK 7,13 GND 74LVC1G08GW -1-GP 1D05V_S0 73.01G08.L04 2nd = 73.7SZ08.AAH 3rd = 73.01G08.L03 1D05V_S0 R112 Do Not Stuff 2 DY R113 56R2J-4-GP C266 PM_THRMTRIP-A# 4,7,12 DY B R114 1KR2J-1-GP DY E E H_PW RGD# B C268 SC2D2U16V3KX-GP C 4,12,48 H_PW RGD 1 32 G7922_PW ROK 13,33,43,44 PM_SLP_S3# G7922_PW ROK C Do Not Stuff KBC_THERMALTRIP# 33 Q9 Q10 MMBT2222A-3-GP Do Not Stuff 84.02222.V11 2nd = 84.02222.R11 Do Not Stuff Do Not Stuff 3D3V_S0 SB DY RUN_POW ER_ON 330KR2J-L1-GP R190 Do Not Stuff R119 SCD22U25V3KX-GP 5V_AUX_S5 Q13 NDS0610-NL-GP DCBATOUT C379 10KR2J-3-GP 3D3V_AUX_S5_EN Do Not Stuff 2nd = 74.09198.Q7F DY Do Not Stuff C375 G NC#4 5V_S5 5V_S0 VOUT VIN GND EN Do Not Stuff Do Not Stuff DY 1 D8 33,42,48 S5_ENABLE 83.00016.B11 BAS16-1-GP 2nd = 83.00016.F11 RSMRST# 32,33 UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size RUN POWER and 3D3V_AUX_S5 Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 Sheet 39 of 51 CPU_CORE ISL6266A VID0 D VID1 VID2 VID3 VID4 VID5 VID6 VID Setting Input Power Output Signal VID0(I / 3.3V) PGOOD VGATE_PWRGD DCBATOUT_51125 RT9018A 1D5V_S0 Output Power VIN 5V(O) 1D8V_S3 5V_S5 (6A) VIN 1D5V_S0 (2.5A) 1D5V(O) D VID1(I / 3.3V) S5_ENABLE VID2(I / 3.3V) VID3(I / 3.3V) Output Power VID4(I / 3.3V) VCC_CORE_PWR(O) VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V Input Signal 3D3V(O) EN0 5V(O) Output Signal PGOOD 3D3V(O) VID5(I / 3.3V) 3D3V_S5 (6A) PM_SLP_S3# EN CPUCORE_ON PGOOD 5V_AUX_S5 RT9026 3D3V_AUX_S5 5V_S5 0D9V_S0 VIN 1D8V_S3 VLDOIN VID6(I / 3.3V) PM_SLP_S4# Input Signal CPUCORE_ON TPS51125 5V/3D3V EN (I / 3.3V) 0D9V_S3 (1A) VTT S3 0D9V_S3_1 VTTREF S5 C C Voltage Sense VCC_SENSE VSS_SENSE VSEN(I / Vcore) RGND(I / Vcore) Input Power DCBATOUT_6266A 5V_S0 3D3V_S0 VCC(I) Charger BQ24745 VCC(I) Input Signal VCC(I) CHG_ON# B 24750_CELLS TPS51124 1D8V/1D05V 5V_S5 DCBATOUT_51124 PM_SLP_S4# PM_SLP_S3# A Input Power VCC Input Signal 1D8V (O) 1D05V(O) 1D8V_S3 (10A) AD+ EN1 Input Signal AD_OFF EN2 Output Power ACN BT+ VOUT (O) VOUT (O) Output Signal (I) B AD_IA SRSET CELLS Adapter 1D05V_S0 (15A) AC_IN# ACGOOD# CHGEN# Input Power Output Power VDD Output Signal (O) AD_IN# DCBATOUT UMA Two Phase Wistron Corporation CPUCORE_ON Output Signal Input Power PGOOD1 AD_JK PGOOD2 5V_AUX_S5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Output Power VCC(I) VCC(O) Title AD+ Power Sequence Logic Size B VCC(I) Document Number Date: Monday, November 24, 2008 Rev HM40-MV Sheet SB 40 of 51 A 2 1 2 2 1 2 1 2 VCC_CORE B one phase TC3 2 68.R3610.20ACAP 2nd = 68.R3610.20C G60 Do Not Stuff 1 L-D36UH-1-GP U36 BSC057N03MSG-GP SA 10R2F-L-GP C31 SC1U25V3KX-1-GP U6 one phase 5V_S0 TC1 CAP BSC057N03MSG-GP DY DY C316 Do Not Stuff L9 6266A_PHASE2 5V_S0 R25 C11 Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A 6266A_UGATE2 R20 Do Not Stuff phase DY C312 G59 Do Not Stuff Do Not Stuff Do Not Stuff 2nd = 77.C3371.0512nd = 77.C3371.051 6266A_LGATE2 R31 Do Not Stuff C36 SCD01U25V2KX-3GP 6266A_VSUM 6266A_ISEN2 6266A_ISEN1 Single Phase R47=1.2K, R63=5.6K,R460=0R C33=47p, C49=0.033u, C52=0.1u R27 R26 R29 R28 one phase 3K65R2F-1-GP 6266A_ISEN2_P2_VCORE 10KR2F-2-GP one phase one phase 1R2F-GP 2 10KR2F-2-GP 6266A_ISEN1_P2_VCORE A UMA Two Phase one phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DY=U7,U28,U29,L9,R62,R56,R42, R45,R37,R39,R48,C20 Size A3 1013 modify R162 BSC057N03MSG-GP 26266A_VO SCD22U10V2KX-1GP 2 C310 one phase -1 ISEN1 ISEN2 -1 2008/05/06 24 6266A_ISEN223 VDD GND 22 6266A_VDD 21 one phase VID1 VID2 VID3 VID4 VID5 VSUM VIN 6266A_VIN 20 C33 DCBATOUT_6266A one phase C34 6266A_ISEN1 6266A_ISEN2_P1_VCORE R156 6266A_BOOT2 26266A_BOOT2_R 2D2R2J-GP 1 R162 NTC-10K-26-GP 2 6266A_VSUM_R_VO 10KR2F-2-GP U34 BSC120N03MS-G-GP one phase 1R2F-GP R34 6266A_UGATE2 R35 28 R30 2K61R2F-1-GP R32 11KR2F-L-GP PHASE2 6266A_ISEN2 C329 SCD22U25V3KX-GP 2 6266A_VO 6266A_PHASE2 6266A_VO 1 C43 1 6266A_D0 37 6266A_D1 38 6266A_D2 39 6266A_D3 40 6266A_D4 41 6266A_D5 42 VO 18 6266A_VO 6266A_VSUM 19 6266A_DFB 17 DFB DROOP RTN 6266A_RTN 15 16266A_DROOP 16 1 2 10KR2F-2-GP one phase Do Not Stuff 1 R36 Do Not Stuff 6266A_ISEN1 SC2D2U16V3KX-GP 20081121 SCD033U25V3KX-GP 6266A_VO S S S G C41 A C45 SCD22U50V3ZY-1GP H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 6266A_D6 6266A_VR_ON 44 43 VID6 VR_ON VID0 29 G58 Do Not Stuff TC2 CAP 6266A_ISEN1_P1_VCORE D D D D 6266A_VSUM PGND2 S S S G SB 6266A_LGATE2 D D D D VSS_SENSE C28 SC330P50V2KX-3GP 0R2J-2-GP 2 3K65R2F-1-GP C29 SCD33U10V3KX-3GP VCC_SENSE 0R2J-2-GP R22 5V_S0 one phase 10R3F-GP SCD01U25V2KX-3GP 20080930 R33 SCD22U10V2KX-1GP R24 C37 SC180P50V2JN-1GP POWER SB SB 20081121 C35 SC330P50V2KX-3GP R144 0R2J-2-GP R143 0R2J-2-GP R139 0R2J-2-GP R138 0R2J-2-GP R146 0R2J-2-GP R142 0R2J-2-GP R137 0R2J-2-GP R136 0R2J-2-GP 0R2J-2-GP 1 6266A_DPRSLPVR R145 DPRSTP# DPRSLPVR 48 VSEN VDIFF R18 DY R21 31 30 25 2 R16 Do Not Stuff PVCC DCBATOUT_6266A TC20 Do Not Stuff Do Not Stuff 2nd = 77.C3371.051 2nd = 77.C3371.051 6266A_VSUM C327 LGATE2 NC#25 R23 G57 Do Not Stuff 6266A_ LGATE1 C321 SCD22U25V3KX-GP TC4 CAP C FB2 1KR2F-3-GP 6266A_SOFT 1KR2F-3-GP 6266A_ LGATE1 26 2K87R2F-1-GP R15 32 BOOT2 R14 1KR2F-3-GP one phase C32 6266A_FB2_R 100R2F-L1-GP-U SC2200P50V2KX-2GP 33 68.R3610.20A 2nd = 68.R3610.20C Do Not Stuff SC270P50V2KX-1GP PGND1 LGATE1 L-D36UH-1-GP SC10U25V6KX-1GP C24 6266A_PHASE1 UGATE2 6266A_FB2 12 PHASE1 34 FB COMP 6266A_VSEN14 11 36 35 27 6266A_VDIFF B 47 49 GND 6266A_FB VW U37 Do Not Stuff 6266A_COMP_R 97K6R2F-GP 10K5R2F-GP OCSET 6266A_VDIFF13 R13 SC100P50V2JN-3GP BOOT1 UGATE1 R151 6266A_BOOT1 6266A_BOOT1_R 2D2R2J-GP 6266A_UGATE1 S S S G R19 6266A_COMP 10 POWER SB D D D D R17 6266A_DPRSTP# R140 2 POWER SA SOFT U7 BSC057N03MSG-GP Id=19.5A Qg=21.5~33nC, Rdson=5.5~6.7mohm 74.06266.073 NTC VCC_CORE Do Not Stuff 6266A_NTC R161 26266A_NTC_R1 R155 NTC-470K-8-GP 4K02R2F-GP C328 C325 6266A_SOFT SCD015U50V3KX-GP SCD01U25V2KX-3GP 6266A_VO 26266A_OCSET R157 12KR3F-GP 1013 modify R161 C22 6266A_VW SC1000P50V3JN-GP ISL6266AHRZ-GP SE330U2VDM-L-GP CPU_PROCHOT#_R D L8 6266A_PHASE1 PSI# 6266A_PMON_R 6266A_PMON PMON R150 4K99R2F-L-GP SCD1U25V3KX-GP 26266A_RBIAS4 RBIAS R152 147KR2F-GP VR_TT# C C25 PGOOD DY C317 Do Not Stuff Vcc_core Iomax=38A Do Not Stuff C320 6266A_UGATE1 S S S G 0R2J-2-GP R1491 26266A_PSI# PSI# DY C313 D D D D C311 Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A S S S G 20080930 C12 DY 20080930 U5 R148 1K91R2F-1-GP 13,32 VGATE_PW RGD U38 BSC120N03MS-G-GP D D D D 6266A_3V3 3D3V_S0 20081117 46 SCD1U10V2KX-4GP 45 R147 R147 2 DY 499R2F-2-GP C314 79.10712.L02 Do Not Stuff 2nd = 79.10112.3JL 1D05V_S0 R154 68R2-GP Do Not Stuff Do Not Stuff G47 3V3 2 SE100U25VM-L1-GP Do Not Stuff TC18 SC10U25V6KX-1GP Do Not Stuff G49 Do Not Stuff G51 H_VID[6 0] Do Not Stuff R141 10R3F-GP S S S G Do Not Stuff G54 2008/05/06 43,44 D D D D DY Do Not Stuff G50 TC17 Do Not Stuff CPUCORE_ON Do Not Stuff 1 Do Not Stuff G52 D 3D3V_S0 G48 PM_DPRSLPVR 7,13 CLK_EN# G53 4,7,12 H_DPRSTP# DCBATOUT_6266A DCBATOUT_6266A DCBATOUT DCBATOUT_6266A DCBATOUT Date: ISL6266A_CPU_CORE Document Number Rev SB HM40-MV Monday, December 01, 2008 Sheet 41 of 51 POWER SA Do Not Stuff G43 Do Not Stuff G12 Do Not Stuff G44 Do Not Stuff G38 Do Not Stuff Do Not Stuff 4 5 6 51125_ENTIP1 51125_ENTIP2 C521 2N7002DW -1-GP R268 110KR3F-GP C519 R275 120KR3F-GP SB 1121 modify R275 D Do Not Stuff G36 51125_ENTIP1 2N7002DW -1-GP DY Do Not Stuff G83 S5_ENABLE 33,39,48 Do Not Stuff G34 Do Not Stuff G10 DY Do Not Stuff G75 Do Not Stuff G41 51125_ENTIP2 33,39,48 S5_ENABLE Do Not Stuff G35 Q26 RN59 SRN100KJ-6-GP Do Not Stuff G74 Q25 Do Not Stuff G11 5V_S5 G37 1 Do Not Stuff G46 5V_PW R 5V_AUX_S5 Do Not Stuff G40 2 Do Not Stuff G45 Do Not Stuff 3D3V_S5 G30 Do Not Stuff 79.68612.30L 2nd = 79.68612.L01 3D3V_PW R TC30 SE68U25VM-3-GP D DCBATOUT_51125 G73 2 DCBATOUT Do Not Stuff G31 Do Not Stuff G32 TC13 Do Not Stuff Do Not Stuff 1020 delete C537 for Power demand 20081117 DY DCBATOUT_51125 DCBATOUT_51125 DCBATOUT_51125 51125_DRVL1 VFB2 VFB1 51125_FB1 TONSEL GND 25 14 SKIPSEL VCLK 18 DY Do Not Stuff 51125_VREF DY Do Not Stuff C524 SC10U10V5KX-2GP R283 2 Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm R273 DY Do Not Stuff C518 3D3V_S5 Do Not Stuff 5V_AUX_S5 DY 1013 modify TC11 and add TC12 51125_FB1_R DY SB 1118 delete TC12 R266 20KR2F-L-GP DY Close to VFB Pin (pin2) C534 SC10U10V5KX-2GP A UMA Two Phase R281 Close to VFB Pin (pin5) 3D3V_AUX_S5 B R270 30KR2F-GP R276 Do Not Stuff Do Not Stuff C283 79.22710.6AL 2nd = 77.92271.021 15V_AUX_S5_51125 R261 3D3V_AUX_S5 S Do Not Stuff G80 Do Not Stuff 3D3V_AUX_S5_5_51125 G79 G 51125_VCLK VREG5 74.51125.073 51125_ENTIP1 GND TPS51125RGER-GP R264 Do Not Stuff 2 51125_PGOOD VREF 51125_SKIPSEL 3D3V_AUX_S5 A 23 51125_TONSEL PGOOD ENTRIP1 15 51125_FB2_R C516 DYDo Not Stuff C517 ENTRIP2 VREG3 Id=7.7A Qg=8.5~13nC R262 Do Not Stuff Rdson=16.5~21mohm DY EN0 TC11 G39 51125_EN 13 820KR2F-GP 51125_ENTIP2 84.04812.A37 2nd = 84.08878.037 51125_VREF 51125_VREF D D D D 51125_FB2 17 2 24 SE220U6D3VM-7GP VO1 Do Not Stuff R280 G SCD22U6D3V2KX-1GP R269 10KR2F-2-GP VO2 68.3R310.20A 2nd = 68.3R31A.10E D Do Not Stuff S 77.C2271.00L 2nd = 77.22271.27L R265 6K65R2F-GP SI4812BDY-T1-E3-GP 84.04812.A37 2nd = 84.08878.037 D D D D IND-3D3UH-57GP U29 51125_VO1 G S S S SI4812BDY-T1-E3-GP G42 19 51125_VO2 LL1 DRVL1 5V_PW R 2 DRVL2 Iomax=5A L6 1 12 51125_LL1 LL2 51125_DRVL2 U23 51125_DRVH1 20 D D D D TC8 D Do Not Stuff ST220U6D3VDM-15GP Do Not Stuff B DY C287 21 Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A SI4800BDY-T1 S 11 G 51125_LL2 IND-3D3UH-57GP VBST1 DRVH1 DRVH2 10 51125_VBST1 VBST2 51125_DRVH2 22 DY SCD1U25V3KX-GP L15 DY C G 51125_VBST2 G S S S C529 SCD1U25V3KX-GP 3D3V_PW R 68.3R310.20AS 2nd = 68.3R31A.10E C528 VIN 84.04800.D37 2nd = 84.08884.037 G S S S Iomax=5A D U28 U47 84.04800.D37 2nd = 84.08884.037 Id=7A Qg=8.7~13nC Rdson=23~30mohm C294 G S S S 16 D D D D U22 SI4800BDY-T1 C299 1 2 D C301 Do Not Stuff Id=7A Qg=8.7~13nC Rdson=23~30mohm DY Do Not Stuff C295 Do Not Stuff DY SC10U25V6KX-1GP Do Not Stuff Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A C508 SC10U25V6KX-1GP C298 C SCD01U50V2KX-1GP C533 Wistron Corporation 0R2J-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R282 DY Title Do Not Stuff Size A3 Date: DCDC 5V/3D3V (TPS51125) Document Number Rev SB HM40-MV Monday, December 01, 2008 Sheet 42 of 51 1D5V_S0 Iomax=2.5A 1D8V_S3 DY R76 PM_SLP_S3# 13,33,39,44 PM_SLP_S3# SC10U10V5KX-2GP Do Not Stuff D C150 C151 D G6 15912_EN_U111 Do Not Stuff Do Not Stuff G8 Do Not Stuff G7 Do Not Stuff G5 Vo(cal.)=1.5024V 20081001 1D5V_LDO 3D3V_S0 1D5V_LDO C158 5912_FB_U111 G966-25ADJF1UF-GP-U SC1U16V3KX-2GP R75 20K5R2F-GP DY Do Not Stuff C148 NC#5 ADJ VEN POK 5912_POK_U111 1 Do Not Stuff C141 C R77 41,44 CPUCORE_ON C C137 2 R74 18KR2J-GP GND GND 1D5V_S0 Do Not Stuff VO VIN VPP SC10U10V5KX-2GP SC100P50V2JN-3GP 5V_S5 R78 2K2R2J-2-GP 1 U13 74.0G966.03D 2nd = 74.09018.A3D Vo=0.8*(1+(R1/R2)) B B 20081001 1016 modify U45 G78 10 9026_S5 9026_S3 VIN S5# GND S3# VTTREF VDDQSNS VLDOIN VTT PGND VTTSNS Do Not Stuff G76 2 Do Not Stuff 74.02997.A79 2nd = 74.09026.079 C509 SC10U10V5KX-2GP G2997BP71U-GP C513 SC1U10V2KX-1GP DDR_VREF_S3_1 R267 R263 Do Not Stuff Do Not Stuff Do Not Stuff G77 U45 13,33,44 PM_SLP_S4# DDR_VREF_S3 DDR_VREF_PW R C523 SCD1U10V2KX-4GP C522 SC10U10V5KX-2GP C520 SC1U10V3KX-3GP Iomax=1A OCP>2A 1D8V_S3 5V_S5 C512 SC10U10V5KX-2GP UMA Two Phase A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Date: Document Number 1D5V & 0D9V Rev SB HM40-MV Monday, December 01, 2008 Sheet 43 of 51 1D8V_S3 1D8V_PW R VO1 VO2 2 SCD1U16V2KX-3GP 51124_V5FILT SB GND OPEN DY 2 1 DY C284 51124_VFB2 C536 R289 30KR2F-GP 360k/CH1 420k/CH2 300k/CH1 360k/CH2 SB 1128 add TC25 DY Vout=0.758V*(R1+R2)/R2 > PWM mode Vout=0.764V*(R1+R2)/R2 > Skip Mode Do Not Stuff 2nd = 79.3971V.E0L Do Not Stuff G66 Do Not Stuff UMA Two Phase A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Date: Do Not Stuff G14 Do Not Stuff G15 TC25 1017 add TC25 Do Not Stuff G13 20081117 Do Not Stuff A 240k/CH1 300k/CH2 Do Not Stuff G16 V5FILT 1D05V_S0 TONSEL TC9 1D05V Iomax=14A OCP>24A 1127 modify U27 B Do Not Stuff G17 77.23371.13L 2nd = 77.C3371.10L Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm 84.01712.037 1 U27 AOL1712-GP Do Not Stuff G64 1121 modify L16,R286 1D05V_PW R 2 Do Not Stuff 51124_VBST2 R287 Do Not Stuff Do Not Stuff G63 ST330U2D5VDM-9GP C526 DY 1D05V_S0 Do Not Stuff G62 SB R286 11K8R2F-GP S S S G Do Not Stuff L16 IND-D88UH-GP DY R288 1 Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A Do Not Stuff 51124_VBST1 SCD1U16V2KX-3GP 51124_LL2 C Do Not Stuff G23 C296 DY DY 84.01426.037 2nd = 84.07686.037 Id=7A Qg=8.7~13nC Rdson=23~30mohm Do Not Stuff TPS51124RGER-GPU1 C510 Do Not Stuff 2 2 C514 SC10U25V6KX-1GP D D D D 51124_LL1 1 G S S S 1 24 U26 AOL1426-GP 20081121 C527 Do Not Stuff G24 G65 17 14 1 51124_DRVH2 51124_LL2 51124_DRVL2 10 11 12 74.51124.073 R272 10KR2F-2-GP 1121 modify R271,R272 77.23371.L01 2nd = 77.C3371.10L 1D05V_PW R DRVH2 LL2 DRVL2 S S S G SB Do Not Stuff G27 20081117 51124_TONSEL R271 19K6R3F-GP Do Not Stuff G29 DCBATOUT_51124 51124_TRIP1 51124_TRIP2 B DY Do Not Stuff G26 TC10 1013 modify TC10 and add TC26 D D D D BC1 Do Not Stuff 51124_DRVH1 51124_LL1 51124_DRVL1 21 20 19 Do Not Stuff G18 1D8V Iomax=10A OCP>15A Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm 84.04812.A37 2nd = 84.08878.037 C532 SC1000P50V3JN-GP C282 R290 21K5R3F-GP GND GND PGND2 PGND1 PGOOD1 PGOOD2 EN1 EN2 25 13 18 DRVH1 LL1 DRVL1 TONSEL 23 VBST1 VBST2 51124_EN1 51124_EN2 0R2J-2-GP DY1 VFB1 VFB2 V5FILT V5IN R277 U25 SI4812BDY-T1-E3-GP R284 Do Not Stuff Do Not Stuff G20 Do Not Stuff 15 16 TRIP1 TRIP2 20080930 51124_V5FILT 22 BC2 Do Not Stuff 51124_VFB1 DY1 SC1U10V3KX-3GPU46 2 13,33,39,43 PM_SLP_S3# 1D05V_PW R 1D8V_PW R 51124_VFB2 51124_VFB1 C300 R278 0R2J-2-GP DY D D D D 51124RGER_PG1 51124RGER_PG2 R274 3D3R3J-L-GP C C525 SC4D7U10V5KX-1GP Do Not Stuff G19 SE330U2D5VDM-LGP R285 30KR2F-GP C535 2 IND-1D5UH-34-GP C531 Do Not Stuff Do Not Stuff 41,43 DY Do Not Stuff 5V_S5 C297 DY 1D8V_PW R 68.1R510.10J 2nd = 68.1R51A.10A L17 CPUCORE_ON Do Not Stuff Id=7A Qg=8.7~13nC Rdson=23~30mohm C515 Do Not Stuff D Do Not Stuff G22 Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A 2008/06/16 R279 Do Not Stuff C511 SC10U25V6KX-1GP 84.04800.D37 2nd = 84.08884.037 20081117 Do Not Stuff G72 Do Not Stuff G21 DY G S S S Do Not Stuff G70 U24 SI4800BDY-T1 D D D D 79.68612.30L 2nd = 79.68612.L01 Do Not Stuff G25 Do Not Stuff Do Not Stuff G67 13,33,43 PM_SLP_S4# DCBATOUT_51124 TC29 SE68U25VM-3-GP TC28 Do Not Stuff I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Do Not Stuff G68 2 DY 79.3971V.6AL 2nd = 79.3971V.E0L TC26 SE390U2D5VM-2GP Do Not Stuff G69 D SB 1128 add TC26 Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin)) G71 1D8V_S3 G28 DCBATOUT_51124 DCBATOUT TPS51124_1D8V_1D05V Document Number Rev SB HM40-MV Friday, November 28, 2008 Sheet 44 of 51 A B C D E Adaptor in to generate DCBATOUT DC1 SB 1121 add the part(EC88) for EMI demand GND NP1 SB 1125 add the part(EC91) for EMI demand 84.04407.F37 2nd = 84.04433.A37 1013 modify U2 R6 100KR2J-1-GP 2 R2 DTC124EUB-GP 84.00124.T1K 2nd = 84.00124.N1K 3rd = 84.00124.K1K R1 AD_OFF C10 SC1U50V5ZY-1-GP DTA124EUB-GP Q4 1 D D D D Q3 AD_OFF#_JK 33 R7 200KR2F-L-GP U2 S S S G AO4407A-GP K AD+_2 A DY 1 2 1022 modify DC1 DY C5 D1 SCD1U50V3ZY-GP P6SMBJ20A-GP 83.P6SMB.AAG 2nd = 83.P6SBM.AAG R1 22.10037.F11 EC91 Do Not Stuff DC-JACK131-GP EC88 Do Not Stuff SCD1U50V3KX-GP EC11 R2 AD+ AD_JK 1016 modify Q3 1016 modify Q4 3 84.00124.S1K 2nd = 84.00124.M1K 3rd = 84.00124.H1K BATA_SDA_1 48 BATA_SCL_1 48 BAT_IN#_1 48 BATTERY CONNECTOR SB 1127 modify BAT1 BAT1 2 RN4 33,46 BAT_SDA 33,46 BAT_SCL 33 BAT_IN# 1 EC50 EC51 DY DY DY 1 2 2 1 1 K DY EL2 Do Not Stuff A EL1 Do Not Stuff EL3 Do Not Stuff EC52 Do Not Stuff EC53 SB DY Do Not Stuff SB MLVS0402M04-GP DY Do Not Stuff EC14 SCD1U50V3ZY-GP DY BATA_SDA_1 BATA_SCL_1 BAT_IN#_1 SRN33J-7-GP BT+ EC13 SCD1U50V3ZY-GP D2 Do Not Stuff GND GND GND GND DAT CLK BAT_IN BT+2 BT+1 SYN-CON7-40-GP 20.81171.007 UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 46 BATT_SENSE 1119 modify EC52 and EL3 R8 Do Not Stuff Title AD/BATT CONN Size Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 A B C D Sheet 45 of E 51 1013 modify U3 DCBATOUT R11 100KR2J-1-GP 2 G S S S VICM SI4800BDY-T1 SCD1U50V3KX-GP NC#16 16 VFB 15 BQ24745RHDR-GP BATT_SENSE BATT_SENSE 45 C318 C18 C19 C322 C323 B MAX8731A_CSIP MAX8731A_CSIN C338 SC1U10V3KX-3GP FBO EAI EAO VREF CE GND GND BQ24745_EAI BQ24745_EAO BQ24745_VREF BQ24745_CHG_ON 12 29 74.24745.073 C364 SCD1U25V2ZY-1GP 2 C341 SC56P50V2JN-2GP C337 R167 SC2200P50V2KX-2GP 7K5R2F-1-GP 1BQ24745_EAO_RC2 C348 SC220P50V2KX-3GP BQ24745_FBO_RC R171 200KR2F-L-GP 84.04800.D37 2nd = 84.08884.037 C365 R166 2BQ24745_FBO 4K7R2J-2-GP 2 18 17 G55 Do Not Stuff SC150P50V2JN-3GP CSOP CSON G56 Do Not Stuff CHG_AGND BQ24745_IINP 68.5R610.10I 2nd = 68.5R610.201 U39 CHG_AGND NC#14 D01R2512F-4-GP SCD1U50V3KX-GP 14 1 24745_LOW _G BT+_R IND-5D6UH-32-GP SC10U25V6KX-1GP 19 SC10U25V6KX-1GP PGND BQ24745_LX1 R160 SC10U25V6KX-1GP 20 BT+ L7 C351 SCD1U50V3KX-GP SC10U25V6KX-1GP LGATE SI4800BDY-T1 D D D D CHG_AGND 23 C DY SCL PHASE DY 83.R0203.08F 2nd = 83.R2003.A8M 24745_HIGH_G ACOK SDA CH520S-30PT-GP SC1U10V3KX-3GP BQ24745_BST BQ24745_VDDP 24 C367 A UGATE D12 K 25 21 BOOT VDDP BQ24745_CSSN TP47 D D D D 27 26 DY G S S S VDDSMB U32 C319 Do Not Stuff CSSN ICOUT ACIN 84.04800.D37 2nd = 84.08884.037 C17 33,45 BAT_SDA 28 C331 10 CSSP C315 C350 SC1U10V3KX-3GP 33,45 BAT_SCL SCD1U25V3KX-GP AC_OK C344 SCD1U50V3KX-GP CHG_AGND R183 2BQ24745_ACOK 13 Do Not Stuff DCBATOUT 2 11 DCIN Do Not Stuff 22 Do Not Stuff U41 SCD1U50V3KX-GP CHG_AGND BQ24745_ACIN Do Not Stuff C347 C340 BQ24745_CSSP 3D3V_AUX_S5 C336 D POWER SB BQ24745_DCIN AD_IA 84.04433.A37 2nd = 84.04407.F37 SC10U25V6KX-1GP SC1U25V5KX-1GP AC_OK C 33 D D D D R153 470KR2J-2-GP C358 R164 309KR3F-GP C342 SCD01U50V2KX-1GP Do Not Stuff 83.00400.C1F 2nd = 83.1S400.A2F G4 K AD+ G3 A 1016 modify D13 C324 SCD1U25V2ZY-1GP D13 1SS400GPT-GP Q2 2N7002DW -1-GP B BT+ AO4433-GP AD+ 20080605 DC_IN_D R172 Do Not Stuff U31 S S S G AD+ D01R2512F-4-GP R12 49K9R2F-L-GP AD+_G_2 AD+_G_1 R169 49K9R2F-L-GP R9 AD+_TO_SYS 84.04433.A37 2nd = 84.04407.F37 R10 10KR2F-2-GP 1013 modify U31 DCBATOUT AO4433-GP D EC54 SCD1U50V3KX-GP 1 ICREF U3 S S S G D D D D NEAR AD+ R163 Do Not Stuff CHG_AGND CHG_AGND CHG_AGND BQ24745_VREF RN43 3D3V_AUX_S5 AC_OK CHG_ON# AC_IN# BQ24745_CHG_ON Q20 A SRN100KJ-8-GP-U C345 DY AC_OK UMA Two Phase CHG_ON# CHG_ON# AC_IN# Do Not Stuff BQ24745_CHG_ON 33 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C AC_IN# to KBC Title 2N7002DW -1-GP AC_IN# C339 SC1U10V3KX-3GP Size A3 Date: A 33 BQ24745 Charger Document Number Rev SB HM40-MV Monday, December 01, 2008 Sheet 46 of 51 5V_S0 5V_S0 1020 delete TC14,TC15 11 TSAHCT125PW -GP U8D TC24 TSAHCT125PW -GP D 73.74125.L13 2nd = 73.74125.L12 73.74125.L13 2nd = 73.74125.L12 1117 delete TC19 SE100U25VM-L1-GP U8C SB 12 13 14 10 14 DCBATOUT D 79.10712.L02 2nd = 79.10112.3JL 1016 modify U32 1017 add these parts(EC10,EC12,EC15~EC17,EC86) for EMI demand SB 1020 add the part(EC86) for EMI demand 1125 add the part(EC90) for EMI demand 1121 add the part(EC89) for EMI demand 1128 add EC94,EC95 for EMI demand 1D8V_S3 2 DY 2 1 1 2 2 DY EC86 EC95 Do Not Stuff DY EC94 Do Not Stuff DY EC90 Do Not Stuff EC89 Do Not Stuff DY EC16 Do Not Stuff Do Not Stuff DY EC17 SCD1U25V2ZY-1GP EC10 SCD1U25V2ZY-1GP Do Not Stuff C EC12 Do Not Stuff EC15 1 1 DCBATOUT DY DY C 1016 add GND1 and GND2 for EMI demand 1017 add GND3 and modify GND2 for EMI demand 34.42Y01.011 GND7 Do Not Stuff DY Do Not Stuff 1 1 GND4 Do Not Stuff DY Do Not Stuff GND8 Do Not Stuff DY Do Not Stuff B H17 Do Not Stuff Do Not Stuff Do Not Stuff H30 Do Not Stuff 1 H29 Do Not Stuff Do Not Stuff H43 UMA Two Phase A Wistron Corporation Do Not Stuff H28 Do Not Stuff 1 1 H8 1 Do Not Stuff H7 H27 Do Not Stuff Do Not Stuff Do Not Stuff H26 Do Not Stuff Do Not Stuff H6 Do Not Stuff H24 Do Not Stuff 1 H23 Do Not Stuff Do Not Stuff Do Not Stuff H5 Do Not Stuff 34.49U23.001 SB 1128 Add GND4,GND7,GND8 H22 Do Not Stuff Do Not Stuff H4 GND3 SPRING-9-GP SB 1120 remove H31and H32 Do Not Stuff H3 34.4F822.002 1016 modify H31 and H32 H21 Do Not Stuff Do Not Stuff Do Not Stuff H2 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff H1 Do Not Stuff A H20 Do Not Stuff 1 H19 Do Not Stuff GND2 SPRING-51-GP 34.42Y01.011 1016 modify H35~H38 1016 delete H9~H12 H18 Do Not Stuff GND1 SPRING-58-GP 34.4B312.002 TOP H38 34.42Y01.011 H37 1 H36 HOLE355X355R111-S1-GP 34.42Y01.011 CPU HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP B H35 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff SB 1128 Add H43 Size EMI/Spring/Boss Document Number Rev SB HM40-MV Date: Friday, November 28, 2008 Sheet 47 of 51 1 1 SPKR_R+ SPKR_RSPKR_L+ SPKR_L- Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP244 TP243 TP245 TP246 D Touch pad 5V_S0 35 35 35,37 35,37 TP_DATA TP_CLK TP_RIGHT TP_LEFT LED Speaker 27,28 27,28 27,28 27,28 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP109 TP105 TP110 TP114 TP113 5V_S0 36 WLAN_LED#_R 36 TP_LOCK_LED#_R 36 TP_LOCK_BN#_1 36 WIRELESS_BTN#_1 36 CAP_LED#_R 36 NUM_LED#_R 36 MEDIA_LED#_R 36 3D3V_S0 PWRLED#_R 36 KBC_PWRBTN#_1 Do Not Stuff TP88 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP229 TP228 TP230 TP231 TP91 TP90 TP234 1 Do Not Stuff Do Not Stuff TP253 TP252 Do Not Stuff TP254 D SB 1112 remove the signal( STDBY_LED#_R) Battery Keyboard 33 33 33 33 KCOL16 KCOL15 KCOL14 KCOL13 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP127 TP139 TP148 TP146 33 33 33 33 KCOL8 KCOL7 KCOL6 KCOL5 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP98 TP99 TP101 TP100 KCOL4 KCOL3 KCOL2 KCOL1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP118 TP138 TP122 TP123 45 45 45 BATA_SDA_1 BATA_SCL_1 BAT_IN#_1 BT+ BT+ AD_JK 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP16 TP17 TP15 TP14 TP13 1 Do Not Stuff Do Not Stuff TP6 TP5 C C Check test point Do Not Stuff TP237 Do Not Stuff TP240 3D3V_S5 Do Not Stuff TP236 5V_S5 Do Not Stuff TP238 4,12,39 H_PWRGD Do Not Stuff TP241 33,39,42 S5_ENABLE Do Not Stuff TP242 Do Not Stuff TP239 3D3V_S0 33 33 33 33 33 33 33 33 KROW0 KROW7 KROW6 KROW5 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP152 TP154 TP153 TP151 3D3V_AUX_S5 4,6 B 33 33 33 33 KROW4 KROW3 KROW2 KROW1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP94 TP95 TP92 TP97 33 33 33 33 KCOL12 KCOL11 KCOL10 KCOL9 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP260 TP116 TP117 TP102 33 33 KCOL17 KCOL0 1 Do Not Stuff Do Not Stuff TP72 TP87 H_CPURST# B Test Point 放放Dimm Door打打打打打打 FAN Bluetooth A 22 22 22 USB_7USB_7+ 3D3V_BT_S0 1 Do Not Stuff Do Not Stuff Do Not Stuff 32 G7922_FAN_TACH Do Not Stuff TP187 32 G7922_FAN_DRIVE Do Not Stuff TP188 UMA Two Phase TP134 TP136 TP133 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 1017 modify USB signal connection Size AFTE test point Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 Sheet 48 of 51 A 0910 delete F4(Page 18) 0910 update footprint of U15(Page 30) 0910 delete RIGHT1 and LEFT1(Page 33) 0910 modify net names of TP_LEFT and TP_RIGHT(Page 36) 0910 modify test points of AFTE and TPAD D D 0911 modify net name from LPC_RST to PLT_RST1#(Page 24) 0911 add net name(RBIAS,LED_DUPLEX#,SMDATA,SMCLK)(Page 24) 0911 add net name(DVDD_1_8,ACZ_SDATAIN0_R,FLY_P,FLY_N,VREF_LO,VREF_HI)(Page 26) 0911 add net name(EAPD#_R)(Page 27) 0912 modify the schematic of Page 33 0912 delete GMCH_TXB*(Page 7& 18) 0912 add these parts for EMI demand(page 7,18,20,21,23,26,28,29,30,32,33,34,35) 0915 modify net name from 10M/100M/1G_LED# to 10M/100M_LED#(page24,25) 0915 delete these parts for EMI demand(page 30) 0915 add EC34 for EMI demand(page3) 0915 add EC73 for EMI demand(page 12) 0915 modify LEDs port 0916 move net(SPI_WP#) from U9 pin120 to pin25(page33) 0930 modify BLUE1(page22) C C 0930 add 2nd for SPK1, MIC1 and modify LOUT1 (page28) 0930 modify FAN1(page32) 0930 modify TPAD1(page35) 0930 modify KB1(page33) 0930 modify net name for BIOS demand(page33) 1001 delete these parts for EMI demand(ED1~8) 1009 modify net name for GND to AGND(page27) 1009 add R4,R5 for AC decopling(page27) 1009 add R96(page30) 1013 modify TPAD1(page35) 1013 modify U40 from 72.25X16.001 to 72.25X16.A01(page 34) 1013 modify TC11 and add TC12(page42) 1013 modify TC10 and add TC26(page44) 1013 modify U2(page45) B 1013 modify U3 and U31(page 46) B 1013 modify R161 and R162(page41) 1013 modify card1(page 30) 1014 modify these LEDs(LED11,LED12)(page38) 1014 modify these nets(page 26) 1014 modify R258 from 10k to 20k ohm(page26) 1014 add ER5 for EMI deamnd(page3) 1015 modify LCD1 pin define(page 18) 1015 modify the power from 3D3V_S5 to 5V_S5(page38) 1015 modify TPAD1(page35) 1015 modify RN57(page28) 1015 modify F1(page18) UMA Two Phase A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Change List Document Number Rev SB HM40-MV Date: Monday, November 24, 2008 Sheet 49 of 51 1016 modify L1,L2 and L3(page 19) 1016 modify XF1(page 25) 1016 modify RN53 and U10(page 24) 1016 modify U8(page19,47) 1016 modify U4(page 37) 1016 modify U23(page 43) D 1016 modify X2(page12) D 1016 modify X1(page 33) 1016 modify X3(page 3) 1016 modify D13(page 46) 1016 modify D23(page 20) 1016 modify D9(page 39) 1016 modify D4(page 19) 1016 modify Q3 and Q4(page45) 1016 modify Q18(page 36) 1016 modify Q15~Q17(page 36) 1016 modify Q27~Q30(page38) 1016 modify Q6 and Q14(page 32) 1016 modify Q8(PAGE 24) 1016 add GND1 nad GND2 for EMI demand(page 47) C 1016 modify LCD1 pin define(page 18) C 1016 delete H9~H12 and modify H35~H38,H31,H32(page 47) 1017 add these parts for EMI demand(page 47) 1017 delete these parts(EC208~EC210)(page 7) 1017 modify BLUE1(page 22) 1017 modify FAN1(page 32) 1017 modify R291 and R293(page 38) 1017 add U61,R52,EC23 and EC24(page 37) 1017 modify RN60(page37) 1017 add TC25(page 44) 1017 add GND3 and modify GND2 for EMI demand(page 47) 1017 modify USB signal connection(page13,18,22,23,30,31,48) 1020 delete C537 for Power demand(page42) 1020 add the part(EC86) for EMI demand(page 47) 1020 delete U61,R52,EC24 and EC23(page 37) B B 1020 delete TC14,TC15(page 47) 1021 modify TC16(page 31) 1021 delete TC23(page 23) 1021 modify TC5(page 20) 1021 modify and swap these parts(USB1 and USB2)(page 23) 1021 modify SATA1(page 20) 1022 modify DC1(page 45) UMA Two Phase A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Change List Document Number Rev SB HM40-MV Date: Monday, November 24, 2008 Sheet 50 of 51 SA to SB 1127 modify C377(page32) for 1106 modify net connection of RN46 and RN44(page33) for layout demand 1106 modify LED11 and LED12(page38) for fixing issue thermal function 1128 Add H43,GND4,GND7,GND8(page47) for EMI demand 1128 modify LCD1(page18) for cost down 1106 modify LED power from 5V_S5 to 5V_AUX_S5(page38) for customer demand 1112 remove the signal(STDBY_LED#_FR)page38 for customer demand 1128 Add L19(page24) for vender demand 1128 add EC94,EC95 for EMI demand(page47) 1112 remove these signals( STDBY_LED#_FR and STDBY_LED#_R) and R131(page36) for customer demand D D 1112 remove the signal( STDBY_LED#_R)page36 for customer demand 1112 remove the signal( STDBY_LED#_R)and TP253(page48) for customer demand 1113 modify C103 and C106(page24) for crystal issue 1113 modify 2nd of U19(page26) 1113 modify 2nd of U43(page39) 1113 modify 2nd of U44(page10) 1113 modify U48(page22) 1117 delete MDC function(R231,R237,R232,R234)(page12) 1117 delete TC19(page 47) for ME deamnd 1118 modify PCB Ver from SA to SB(page33) 1118 delete TC12(page42) for layout demand 1118 delete TC27(page9) for layout demand 1118 delete R107 and add L18 for cost down 1119 modify R130 and R133(page 36) for LED brightness C 1119 modify EC52 and EL3(page45) for EMI demand C 1119 modify SPK1(page 28) for ME deamnd 1119 add G84 for RTC reset demand 1120 modify EC78for EMI demand((page10) 1120 modify PowerCN1 pin3 and remove EC44(page36) fro LED function 1120 remove H31 and H32(page47)for ME demand 1120 add RN61 and RN62(page3) for layout demand 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 add the net( SATACLKREQ#)(page3,13)for CLK REQ demand 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 modify RN61 and RN62(page3)for CLK REQ demand 1121 add EC87 for EMI demand(page18) 1121 add the part(EC89) for EMI demand(page47) 1121 add the part(EC88) for EMI demand(page45) B 1121 modify R18,C43(page41) for Power demand B 1121 modify R275(page42)for Power demand 1121 modify R271,R272,R286 and L16(page44) for Power demand 1124 modify U42 and delete R182,R185 (page32) for thermal function 1124 modify these names of these nets(G7922_SGND2,G7922_SGND3 ) (page32) for thermal function 1124 add R302(page3) for clock gen function 1125 add the part(EC90) for EMI demand(page47) 1125 add the part(EC91) for EMI demand(page45) 1125 modify R125,R126(page18) for LCD brightness control 1125 modify RN40 and delete RN42(page32) for layout demand 1125 add EC92 and EC93 for EMI demand(page 22) 1126 add these nets (PCIE_REQ_LAN#,PCIE_REQ_MINI#)(page3)for CLK REQ demand 1126 delete R230,R233,R235,R236 and RN63(page12) for removing MDC function 1126 add C541 and modify R101(page26) for codec function 1126 modify RN61 and RN62(page3) for layout demand A UMA Two Phase A 1126 modify EU1,EU2 and add EU3,EU4 for EMI demand(page28) Wistron Corporation 1127 modify CRT1(page19) for customer demand 1127 swap the nets of 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C RN61 and RN62 for layout demand(page3) 1127 modify BAT1(page45) for ME demand Title 1127 modify U27(page44) for power demand Size Change List Document Number Rev SB HM40-MV Date: Monday, December 01, 2008 Sheet 51 of 51 ... ICH9M Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title SMBC_ICH 9LPRS365BKLFT DDR Size A3 Date: Reference Document Number Rev SB HM40- MV Monday,... 800M 1066M UMA Two Phase Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Clock Generator Document Number Rev HM40- MV Date: A SB DMI CLK_PCIE_ICH... BGA479-SKT6-GPU7 62.10079.001 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Document Number CPU (2 of 2) Rev SB HM40- MV Date: A B C D Monday,