A B C D E m o c e u l b p o t p a l w W w Compal Confidential 2 HBL50 Schematics Document Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M (With nVIDIA G73M/72MV) 2005-11-08 REV: 0.3 3 4 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 E of 59 A B C D Compal Confidential m o c e u l b p o t p a l w W w page 47 page uPGA-478 Package DVI-D Conn LCD Conn CRT & TV-out page 23 page 25 H_A#(3 31) LVDS SDVO CH7307C DVI page 14 page 4,5 PSB 533/667MHz H_D#(0 63) page 24 DVI page 25 Clock Generator ICS9LPRS325 Thermal Sensor F75383M Yonah Fan Control Model Name : HBL50 File Name : LA-2921 E Memory BUS(DDRII) Intel 945PM/GM Dual Channel uFCBGA-1466 1.8V DDRII 400/533 LVDS PCI-Express 200pin DDRII-SO-DIMM X2 BANK 0, 1, 2, page 6,7,8,9,10,11 nVidia G73M/(72M)/72MV with 64/128/256MB VRAM DMI New Card Socket page page 15,16,17,18,19,20,21,22 LAN(GbE) BCM5789 37 MINI CARD x2 page 34 PCI BUS 3.3V 33 MHz IDSEL:AD16 (PIRQE#, GNT#2, REQ#2) IDSEL:AD18 (PIRQG/H#, GNT#3, REQ#3) IEEE 1394 VT6311S page 38 IDSEL:AD17 (PIRQF#, GNT#3, REQ#3) Intel ICH7-M IDSEL:AD20 (PIRQA#, GNT#2, REQ#2) Mini PCI socket LAN (10/100) (WLAN) (TV-Tuner) page 34 3.3V ATA-100 page 26,27,28,29 USB port 0, USB port5 USB port HD Audio IDE S-ATA CDROM Conn page 31 ENE CB714 page 32 Bluetooth Conn page 42 page 37 USB port 3, 3.3V 24.576MHz/48Mhz BGA-652 CardBus BCM4401E 3.3V 48MHz USB conn x4 page 36 PCI Express page 12,13 port port MDC 1.5 Conn page 42 HDA Codec ALC883 page 44 page 36 RJ45 1394 Conn page 38 Slot page 35 page 33 in socket S-ATA HDD Conn.page 30 page 33 HDD Conn page SATA-to-IDE SPIF3811-HV096 page 30 30 Audio AMP LPC BUS Subwoofer page 45 page 46 3 RTC CKT ENE KB910Q page 43 page 40 Power On/Off CKT page 43 Super I/O TPM1.2 SMsC LPC47N207 SLB9635 TT 1.2 page 39 Phone Jack x3 page 45 page 39 Switch/B Conn USB port4, page 42 Int.KBD Touch Pad page 43 FIR page 41 TFDU6102-TR3 DC/DC Interface CKT page 48 Power Circuit DC/DC page 49,50,51,52 53,54,55,56 CD-PLAY/B Conn page 42 page 39 BIOS EC I/O Buffer page 41 page 41 MEDIA/B Conn page 42 CIR page 42 4 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 E of 59 A B C D SIGNAL STATE Voltage Rails E SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS 2.5V switched power rail ON OFF OFF Vcc Ra/Rc/Re +3VALW 3.3V always on power rail ON ON ON* Board ID +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON m o c e u l b p o t p a l w W w Full ON Board ID / SKU ID Table for AD channel 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOARD ID Table Board ID External PCI Devices Device IDSEL# CardBus(SD) Interrupts AD20 PIRQA/PIRQB 13 94 AD16 PIRQE LAN(10/100) AD17 PIRQF Mini-PCI(WLAN/TV-Tuner) AD18 PIRQG/PORQH EC SM Bus1 address REQ#/GNT# Device Address Smart Battery 0001 011X b EEPROM(24C16/02) 1010 000X b GMT G781-1 1001 101X b EC SM Bus2 address Device SKU ID 1001 100X b ICH7M SM Bus address Device Address Clock Generator (ICS9LPRS325AKLFT_MLF72) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb PCB Revision 0.1 BTO Item BOM Structure VGA PM@ + VGA@ GM@ UMA UMA's DVI 7307@ LAN(10/100) 4401@ 5789@ LAN(GIGA) MINI CARD1 MINI1@ MINI CARD2 MINI2@ SATA-to-IDE 3811@ PATA PATA@ GRAPEVINE GRA@ G72MV Only G72@ G73 Only G73@ VRAM X76@ VRAM 64M 64@ VRAM 128M 64@+128@ VRAM 256M 64@+128@+256@ MEDIA/B MEDIA@ CIR CIR@ FIR FIR@ GENEVA GEN@ LCM LCM@ Sub-woofer SUB@ 5789&5787 8789@ 4401&5789 0189@ VP1020 VP1020@ INTERNAL MIC INTMIC@ 1394 1394@ SATA HDD SATA@ SKU ID Table Address Fintek F75383M BTO Option Table SKU PM GM 2005/06/20 Issued Date 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Compal Electronics, Inc Compal Secret Data Security Classification D Title Notes List Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 E of 59 m o c e u l b p o t p a l w W w H_D#[0 63] JP18A H_A#[3 31] H_A#[3 31] D H_REQ#[0 4] H_REQ#[0 4] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 K3 H2 K2 J3 L5 REQ0# REQ1# REQ2# REQ3# REQ4# L2 V4 ADSTB0# ADSTB1# H_ADSTB#0 H_ADSTB#1 C 14 CLK_CPU_BCLK 14 CLK_CPU_BCLK# A22 A21 H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM# H1 E2 G5 F1 H5 F21 G6 E4 D20 H4 B1 H_LOCK# H_RESET# H_RS#[0 2] H_RS#[0 2] H_IERR# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# T5 T3 T1 T4 B PAD PAD PAD PAD 28 ITP_DBRESET# H_DBSY# 27 H_DPSLP# 27,56 H_DPRSTP# H_DPWR# PAD T2 27 H_PWRGOOD H_CPUSLP# 6,27 H_THERMTRIP# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 F3 F4 G3 G2 AD4 AD3 AD1 AC4 ITP_DBRRESET# C20 E1 B5 E5 D24 ITP_BPM#4 AC2 ITP_BPM#5 AC1 H_PROCHOT# D21 YONAH ADDR GROUP BCLK0 BCLK1 ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET# DATA GROUP HOST CLK CONTROL RS0# RS1# RS2# TRDY# BPM0# BPM1# BPM2# BPM3# DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT# MISC H_PW RGOOD H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST# D6 D7 AC5 AA6 AB3 C26 D25 AB5 AB6 PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST# THERMDA THERMDC A24 A25 C7 THERMDA DIODE THERMDC THERMTRIP# THERMAL D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0 63] +3VS C624 0.1U_0402_16V4Z U37 C625 2200P_0402_50V7K D VDD SCLK EC_SMB_CK2 40 THERMDA D+ SDATA EC_SMB_DA2 40 THERMDC D- ALERT# GND THERM# ADM1032ARMZ-2REEL_MSOP8 F75383M_MSOP8 +1.05VS C DINV0# DINV1# DINV2# DINV3# J26 M26 V23 AC20 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# H23 M24 W24 AD23 G22 N25 Y25 AE24 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 A20M# FERR# IGNNE# INIT# LINT0 LINT1 A6 A5 C4 B3 C6 B4 H_A20M# 27 H_FERR# 27 H_IGNNE# 27 H_INIT# 27 H_INTR 27 H_NMI 27 STPCLK# SMI# D5 A3 H_STPCLK# 27 H_SMI# 27 LEGACY CPU 6 6 ITP_TDI R15 56_0402_5% ITP_TDO R17 56_0402_5% ITP_TMS R16 56_0402_5% H_PROCHOT# R500 75_0402_5% ITP_BPM#5 R18 56_0402_5% H_IERR# R501 56_0402_5% ITP_TRST# R19 56_0402_5% ITP_TCK R20 56_0402_5% TEST1 R513 @ 1K_0402_5% TEST2 R512 B 51_0402_5% 6 6 6 6 FOX_PZ47903-2741-42_YONAH A A Layout Note: THERMDA & THERMDC Trace / Space = 10 / 10 mil 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Yonah (1/2) Size Document Number Custom Rev 0.3 HBL50 LA-2921P Date: Sheet Friday, November 11, 2005 of 59 Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4Ohms with 50 mil spacing Place PU and PD wihin inch of CPU m o c e u l b p o t p a l w W w D 100_0402_1% 100_0402_1% 2 56 VSSSENSE VCCSENSE VSSSENSE 20mils 10U_0805_10V4Z 1 2 VCCA K6 J6 M6 N6 T6 R6 K21 J21 M21 N21 T21 R21 V21 W21 V6 G21 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP 56 PSI# AE6 PSI# CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 AD6 AF5 AE5 AF4 AE3 AF2 AE2 VID0 VID1 VID2 VID3 VID4 VID5 VID6 +1.05VS C626 0.01U_0402_16V7K Layout Note: Place C14 near Pin B26 56 56 56 56 56 56 56 +1.05VS R511 1K_0402_1% C R510 VCCSENSE VSSSENSE B26 +1.5VS C628 AF7 AE7 GTL_REF0 2K_0402_1% 14 CPU_BSEL0 14 CPU_BSEL1 14 CPU_BSEL2 COMP0 COMP1 COMP2 COMP3 +CPU_CORE BSEL2 BSEL1 BSEL0 BCLK 0 133 1 166 B R515 27.4_0402_1% COMP0 R514 54.9_0402_1% COMP1 R13 27.4_0402_1% COMP2 R14 54.9_0402_1% COMP3 AD26 GTLREF B22 B23 C21 BSEL0 BSEL1 BSEL2 R26 U26 U1 V1 COMP0 COMP1 COMP2 COMP3 E7 AB20 AA20 AF20 AE20 AB18 AB17 AA18 AA17 AD18 AD17 AC18 AC17 AF18 AF17 D2 F6 D3 C1 AF1 D22 C23 C24 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 T22 B25 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC +CPU_CORE +CPU_CORE JP18B 56 VCCSENSE R499 R498 YONAH POWER, GROUNG, RESERVED SIGNALS AND NC +CPU_CORE RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AB26 AA25 AD25 AE26 AB23 AC24 AF24 AE23 AA22 AD22 AC21 AF21 AB19 AA19 AD19 AC19 AF19 AE19 AB16 AA16 AD16 AC16 AF16 AE16 AB13 AA14 AD13 AC14 AF13 AE14 AB11 AA11 AD11 AC11 AF11 AE11 AB8 AA8 AD8 AC8 AF8 AE8 AA5 AD5 AC6 AF6 AB4 AC3 AF3 AE4 AB1 AA2 AD2 AE1 B6 C5 F5 E6 H6 J5 M5 L6 P6 R5 V5 U6 Y6 A4 D4 E3 H3 G4 K4 L3 P3 N4 T4 U3 Y3 W4 D1 C2 F2 G1 JP18C x 330uF(9mOhm/3) 1 + C614 + C609 + C621 @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 2 South Side Secondary +CPU_CORE x 330uF(9mOhm/3) 1 + C620 + C608 + C619 @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 2 North Side Secondary +CPU_CORE C31 22U_0805_6.3V6M C33 22U_0805_6.3V6M C35 22U_0805_6.3V6M C32 C30 22U_0805_6.3V6M C28 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer) C26 22U_0805_6.3V6M C24 22U_0805_6.3V6M +CPU_CORE 22U_0805_6.3V6M C618 C623 22U_0805_6.3V6M 22U_0805_6.3V6M C613 C616 C22 22U_0805_6.3V6M C20 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer) +CPU_CORE 22U_0805_6.3V6M C607 C611 22U_0805_6.3V6M C29 22U_0805_6.3V6M C27 C25 22U_0805_6.3V6M C23 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer) +CPU_CORE C21 22U_0805_6.3V6M C19 22U_0805_6.3V6M 22U_0805_6.3V6M C617 C622 22U_0805_6.3V6M C612 C615 22U_0805_6.3V6M C606 C610 2 2 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M (Place these capacitors on North side,Secondary Layer) +CPU-CORE Decoupling SPCAP,Polymer C,uF ESR, mohm 6X330uF 9m ohm/6 1.8nH/6 MLCC 0805 X5R 32X22uF 3m ohm/32 0.6nH/32 ESL,nH +1.05VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AE18 AE17 AB15 AA15 AD15 AC15 AF15 AE15 AB14 AA13 AD14 AC13 AF14 AE13 AB12 AA12 AD12 AC12 AF12 AE12 AB10 AB9 AA10 AA9 AD10 AD9 AC10 AC9 AF10 AF9 AE10 AE9 AB7 AA7 AD7 AC7 B20 A20 F20 E20 B18 B17 A18 A17 D18 D17 C18 C17 F18 F17 E18 E17 B15 A15 D15 C15 F15 E15 B14 A13 D14 C13 F14 E13 B12 A12 D12 C12 F12 E12 B10 B9 A10 A9 D10 D9 C10 C9 F10 F9 E10 E9 B7 A7 F7 FOX_PZ47903-2741-42_YONAH C13 220U_D2_2VMR15 TRACE CLOSELY CPU < 0.5' + 1 C34 C36 C38 0.1U_0402_16V4Z COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Space 25mils (55Ohms) C37 C16 0.1U_0402_16V4Z C18 1 C17 @ 0.1U_0402_16V4Z C15 @ VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS YONAH POWER, GROUND K1 J2 M2 N1 T1 R2 V2 W1 A26 D26 C25 F25 B24 A23 D23 E24 B21 C22 F22 E21 B19 A19 D19 C19 F19 E19 B16 A16 D16 C16 F16 E16 B13 A14 D13 C14 F13 E14 B11 A11 D11 C11 F11 E11 B8 A8 D8 C8 F8 E8 G26 K26 J25 M25 N26 T26 R25 V25 W26 H24 G23 K23 L24 P24 N23 T23 U24 Y24 W23 H21 J22 M22 L21 P21 R22 V22 U21 Y21 D C B FOX_PZ47903-2741-42_YONAH 0.1U_0402_16V4Z A A 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Yonah (2/2) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 of 59 945GM(A-3)(QK56)[QS]: SA0000059D0(ABO!) 945PM(A-3)(QK58)[QS]: SA00000KD70(ABO!) m o c e u l b p o t p a l w W w R532 54.9_0402_1% R530 54.9_0402_1% HVREF0 HVREF1 HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING R529 24.9_0402_1% R531 24.9_0402_1% B HADSTB#0 HADSTB#1 B9 C13 H_ADSTB#0 H_ADSTB#1 HCLKN HCLKP AG1 AG2 CLK_MCH_BCLK# CLK_MCH_BCLK HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 K4 T7 Y5 AC4 K3 T6 AA5 AC5 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 J7 W8 U3 AB10 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 HCPURST# HADS# HTRDY# HDPWR# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# B7 E8 E7 J9 H8 C3 D4 D3 B3 C7 C6 F6 A7 E3 H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRD Y# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP# HRS0# HRS1# HRS2# B4 E6 D6 H_RS#0 H_RS#1 H_RS#2 HDINV#0 HDINV#1 HDINV#2 HDINV#3 DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 28 28 28 28 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 28 28 28 28 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 28 28 28 28 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 H_REQ#[0 4] H_ADSTB#0 H_ADSTB#1 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 R47 R46 4 4 H_RESET# H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR0# H_BNR# H_BPRI# H_DBSY# H_CPUSLP# 1 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 AE37 AF41 AG37 AH41 DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 AC37 AE41 AF37 AG41 DMITXP0 DMITXP1 DMITXP2 DMITXP3 SM_CK0 SM_CK1 SM_CK2 SM_CK3 12 12 13 13 DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# AW35 AT1 AY7 AY40 SM_CK0# SM_CK1# SM_CK2# SM_CK3# 12 12 13 13 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 AU20 AT20 BA29 AY29 SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 DDRA_SCS#0 DDRA_SCS#1 DDRB_SCS#0 DDRB_SCS#1 AW13 AW12 AY21 AW21 SM_CS0# SM_CS1# SM_CS2# SM_CS3# PAD PAD M_OCDOCMP0 M_OCDOCMP1 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 80.6_0402_1% 80.6_0402_1% SMRCOMPN SMRCOMPP SM_OCDCOMP0 SM_OCDCOMP1 BA13 BA12 AY20 AU21 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 AK1 AK41 SMVREF PM_BMBUSY# G28 PM_EXTTS#0 F25 PM_EXTTS#1 H26 H_THERMTRIP# G6 4,27 H_THERMTRIP# GMCH_PWROK AH33 PLTRST_R# AH34 26,28,31,34,39,40 PLT_RST# R128 100_0402_1% K28 26 MCH_ICH_SYNC# 28 PM_BMBUSY# 12,13 PM_EXTTS#0 AG33 AF33 CLK_MCH_3GPLL CLK_MCH_3GPLL# D_REF_CLKN D_REF_CLKP A27 A26 CLK_DREF_96M# CLK_DREF_96M D_REF_SSCLKN D_REF_SSCLKP C40 D41 CLK_DREF_SSC# CLK_DREF_SSC H32 MCH_CLKREQ# CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 CLK_REQ# AL20 AF10 AV9 AT9 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 PAD CFG4 PAD CFG5 CFG6 PAD CFG7 CFG8 PAD CFG9 CFG10 PAD CFG11 CFG12 CFG13 CFG14 PAD CFG15 PAD CFG16 CFG17 PAD CFG18 CFG19 CFG20 G_CLKP G_CLKN AY35 AR1 AW7 AW40 12 12 13 13 +1.8V AC35 AE39 AF35 AG39 DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 T17 T6 4 4 4 4 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 12 12 13 13 12 12 13 13 CLK_MCH_BCLK# 14 CLK_MCH_BCLK 14 DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26 CFG H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 28 28 28 28 AE35 AF39 AG35 AH39 CLK D8 G8 B8 F8 A8 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 Description at page10 U40B DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 A3 A39 A4 A40 AW1 AW41 AY1 BA1 BA2 BA3 BA39 BA40 BA41 C1 AY41 B2 B41 C41 D1 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13 T32 R32 F3 F7 AG11 AF11 H7 J19 A41 A34 D28 D27 A35 NC H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 SM_RCOMPN SM_RCOMPP SM_VREF0 SM_VREF1 PM_BMBUSY# PM_EXTTS0# PM_EXTTS1# PM_THERMTRIP# PWROK RSTIN# PM J13 H_VREF K13 H_XRCOMP E1 H_XSCOMP E2 H_YRCOMP Y1 H_YSCOMP U1 H_SWNG0 E4 H_SWNG1 W1 H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# DDR MUXING +1.05VS HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# DMI C F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 HOST D H_A#[3 31] U40A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 ICH_SYNC# CALISTOGA_FCBGA1466~D PM@ RESERVED H_D#[0 63] MCH_CLKSEL0 14 MCH_CLKSEL1 14 MCH_CLKSEL2 14 T15 T8 CFG5 10 T14 CFG7 10 T11 CFG9 10 T12 CFG11 10 CFG12 10 CFG13 10 T7 T13 CFG16 10 T9 CFG18 10 CFG19 10 CFG20 10 D CLK_MCH_3GPLL 14 CLK_MCH_3GPLL# 14 CLK_DREF_96M# 14 CLK_DREF_96M 14 CLK_DREF_SSC# 14 CLK_DREF_SSC 14 MCH_CLKREQ# 14 C B Layout Note: SMVREF trace width and spacing is 20/20 H_RS#[0 2] GMCH_PWROK +1.8V R127 R130 CALISTOGA_FCBGA1466~D PM@ @ 0_0402_5% VGATE VGATE 14,28,56 0_0402_5% SYS_PWROK SYS_PWROK 28,43 +1.05VS +1.05VS +1.05VS R527 221_0603_1% R528 221_0603_1% 100_0402_1% H_SWNG0 +3VS R578 100_0402_1% R111 10K_0402_5% PM_EXTTS#0 28,56 PM_DPRSLPVR R121 PM_EXTTS#1 0_0402_5% R100 @ 10K_0402_5% A 2005/09/20 H_SWNG1 0.1U_0402_16V4Z C641 R526 100_0402_1% 0.1U_0402_16V4Z C48 R44 100_0402_1% 0.1U_0402_16V4Z C66 H_VREF 200_0603_1% 1 R53 A R60 2 0.1U_0402_16V4Z C46 SMVREF Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20 R577 100_0402_1% 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Calistoga (1/6) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 of 59 m o c e u l b p o t p a l w W w 12 DDRA_SMA[0 13] 12 DDRA_SDM[0 7] DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 C 12 12 12 12 12 12 12 12 DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 12 12 12 12 12 12 12 12 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 AY13 AW14 AY14 AK23 AK24 SA_CAS# SA_RAS# SA_WE# SA_RCVENIN# SA_RCVENOUT# SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 B 12 DDRA_SCAS# 12 DDRA_SRAS# 12 DDRA_SWE# T18 T19 PAD PAD SA_RCVENIN# SA_RCVENOUT# DDRB_SMA[0 13] 13 DDRB_SMA[0 13] DDRA_SMA[0 13] DDR SYS MEMORY A SA_BS0 SA_BS1 SA_BS2 DDRB_SDQ[0 63] 13 DDRB_SDQ[0 63] DDRA_SDQ[0 63] D U40D AU12 AV14 BA20 12 DDRA_SBS0# 12 DDRA_SBS1# 12 DDRA_SBS2# check layout AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8 U40E DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 AT24 AV23 AY28 SB_BS0 SB_BS1 SB_BS2 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 AR24 AU23 AR27 AK16 AK18 SB_CAS# SB_RAS# SB_WE# SB_RCVENIN# SB_RCVENOUT# 13 DDRB_SBS0# 13 DDRB_SBS1# 13 DDRB_SBS2# 13 DDRB_SDM[0 7] 13 13 13 13 13 13 13 13 DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 13 13 13 13 13 13 13 13 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# 13 DDRB_SCAS# 13 DDRB_SRAS# 13 DDRB_SWE# T10 T16 PAD PAD SB_RCVENIN# SB_RCVENOUT# DDR SYS MEMORY B 12 DDRA_SDQ[0 63] D check layout CALISTOGA_FCBGA1466~D PM@ SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3 DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 C B CALISTOGA_FCBGA1466~D PM@ A A 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Calistoga (2/6) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 of 59 D m o c e u l b p o t p a l w W w D U40C GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+ 23 GMCH_TXOUT0+ 23 GMCH_TXOUT1+ 23 GMCH_TXOUT2+ 23 GMCH_TXOUT023 GMCH_TXOUT123 GMCH_TXOUT2- 23 GMCH_TZOUT023 GMCH_TZOUT123 GMCH_TZOUT223 23 23 23 C GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK- R108 GM@ 0_0402_5% LBKLT_EN 15,40 ENBKL 23 GMCH_LCD_CLK 23 GMCH_LCD_DATA 23 GMCH_ENVDD C37 B35 A37 LA_DATA#0 LA_DATA#1 LA_DATA#2 GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+ F30 D29 F28 LB_DATA0 LB_DATA1 LB_DATA2 GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2- G30 D30 F29 LB_DATA#0 LB_DATA#1 LB_DATA#2 GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK- A32 A33 E26 E27 LA_CLK LA_CLK# LB_CLK LB_CLK# D32 J30 H30 H29 G26 G25 F32 B38 C35 C33 C32 LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL A16 C18 A19 TVDAC_A TVDAC_B TVDAC_C J20 TV_IREF GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA R82 TV_IREF 4.99K_0402_1% B16 B18 B19 J29 K30 B 24 GMCH_CRT_VSYNC 24 GMCH_CRT_HSYNC 24 GMCH_CRT_B 24 GMCH_CRT_G 24 GMCH_CRT_R GMCH_CRT_CLK GMCH_CRT_DATA R567 R565 R564 1 150_0402_1% 150_0402_1% 150_0402_1% R91 CRT_IREF 255_0402_1% TV_IRTNA TV_IRTNB TV_IRTNC TV_DCONSEL1 TV_DCONSEL0 C26 C25 DDCCLK DDCDATA H23 G23 E23 D23 C22 B22 A21 B21 VSYNC HSYNC BLUE BLUE# GREEN GREEN# RED RED# J22 CRT 24 GMCH_CRT_CLK 24 GMCH_CRT_DATA TV 24 GMCH_TV_COMPS 24 GMCH_TV_LUMA 24 GMCH_TV_CRMA LA_DATA0 LA_DATA1 LA_DATA2 GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2- LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD LIBG CRT_IREF 10mils +3VS A R122 10K_0402_5% GMCH_LCD_CLK R104 10K_0402_5% GMCH_LCD_DATA R125 10K_0402_5% LCTLB_DATA R117 10K_0402_5% LCTLA_CLK R107 4.7K_0402_5% GMCH_CRT_CLK R94 4.7K_0402_5% GMCH_CRT_DATA R109 100K_0402_5% LBKLT_EN R576 1.5K_0402_1% LIBG R541 150_0402_1% GMCH_TV_COMPS R544 150_0402_1% GMCH_TV_LUMA R563 150_0402_1% GMCH_TV_CRMA EXP_COMPI EXP_COMPO LVDS 23 GMCH_TZOUT0+ 23 GMCH_TZOUT1+ 23 GMCH_TZOUT2+ B37 B34 A36 SDVOCTRL_DATA SDVOCTRL_CLK PCI-EXPRESS GRAPHICS H27 H28 25 SDVO_SDAT 25 SDVO_SCLK D40 D38 PEG_COMP 10mils R138 EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 24.9_0402_1% +1.5VS_PCIE PCIE_MTX_C_GRX_N[0 15] PCIE_MTX_C_GRX_P[0 15] PCIE_GTX_C_MRX_N[0 15] PCIE_GTX_C_MRX_P[0 15] PCIE_MTX_C_GRX_P[0 15] 15 PCIE_GTX_C_MRX_N[0 15] 15 PCIE_GTX_C_MRX_P[0 15] 15 C C715 C710 C708 C706 C704 C702 C700 C743 C698 PM@ 0.1U_0402_16V4Z C713 PM@ 0.1U_0402_16V4Z C733 PM@ 0.1U_0402_16V4Z C732 PM@ 0.1U_0402_16V4Z C729 PM@ 0.1U_0402_16V4Z C727 PM@ 0.1U_0402_16V4Z C725 PM@ 0.1U_0402_16V4Z C723 PM@ 0.1U_0402_16V4Z C697 0.1U_0402_16V4Z C714 0.1U_0402_16V4Z C734 0.1U_0402_16V4Z C731 0.1U_0402_16V4Z C730 0.1U_0402_16V4Z C728 0.1U_0402_16V4Z C726 0.1U_0402_16V4Z C724 0.1U_0402_16V4Z C716 PM@ C711 PM@ C709 PM@ C707 PM@ C705 PM@ C703 PM@ C701 PM@ C744 PM@ PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15 1 1 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 1 1 1 B CALISTOGA_FCBGA1466~D PM@ PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1 C695 C696 7307@ 0.1U_0402_16V4Z 7307@ 0.1U_0402_16V4Z PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P0 C209 C216 7307@ 0.1U_0402_16V4Z 7307@ 0.1U_0402_16V4Z C239 C240 7307@ 0.1U_0402_16V4Z 7307@ 0.1U_0402_16V4Z C241 C242 7307@ 0.1U_0402_16V4Z 7307@ 0.1U_0402_16V4Z C234 C235 7307@ 0.1U_0402_16V4Z 7307@ 0.1U_0402_16V4Z PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P3 2005/06/20 Issued Date 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SDVO_INT# 25 SDVO_INT 25 SDVOB_R# 25 SDVOB_R 25 SDVOB_G# 25 SDVOB_G 25 SDVOB_B# 25 SDVOB_B 25 A SDVOB_CLK# 25 SDVOB_CLK 25 Compal Electronics, Inc Compal Secret Data Security Classification PCIE_MTX_C_GRX_N[0 15] 15 Title Calistoga (3/6) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 of 59 +1.05VS D7 @ RB751V_SOD323 R101 @ 10_0402_5% +2.5VS +1.5VS D6 @ RB751V_SOD323 R93 @ 10_0402_5% +3VS m o c e u l b p o t p a l w W w +2.5VS +1.5VS A AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 E19 F19 C20 D20 E20 F20 C196 0.1U_0402_16V4Z C683 0.1U_0402_16V4Z C722 10U_0805_10V4Z C712 10U_0805_10V4Z C690 330U_D2E_2.5VM +2.5VS 2005/09/21 +3VS_TVDACB close pin G41 + C887 2 220U_D2_4VM CRTDAC: Route caps within 250mil of Alviso Route FB within 3" of Calistoga +3VS_TVDACC (120mA) +3VS_TVDACA +3VS_TVDACB +3VS_TVDACC 1 2 +3VS_TVDACA +3VS L5 MBK1608301YZF_0603 2005/09/19 + C49 220U_D2_4VM C +2.5VS +3VS_TVBG +3VS L7 MBK1608301YZF_0603 C85 0.1U_0402_16V4Z C194 0.1U_0402_16V4Z 2 +3VS L4 MBK1608301YZF_0603 1 AH1 (150mA) +1.5VS AH2 close pin A38 (20mA) 2 2 +1.5VS_3GPLL +1.5VS R112 0_0603_5% 1 @ +1.5VS_MPLL R517 0_0603_5% 45mA Max +1.5VS +1.5VS_TVDAC R568 0_0603_5% 1 2 @ +1.5VS_HPLL +1.5VS 2 B R516 0_0603_5% 45mA Max +1.5VS C672 0.1U_0402_16V4Z 1 C94 0.022U_0402_16V7K AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 +3VS (40mA) PCI-E/MEM/PSB PLL decoupling C119 0.1U_0402_16V4Z A23 B23 B25 +3VS R90 0_0603_5% +1.5VS_TVDAC C140 0.1U_0402_16V4Z +3VS_TVBG D21 (24mA) H19 C139 10U_0805_10V4Z A28 B28 C28 C141 0.1U_0402_16V4Z VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 C93 0.022U_0402_16V7K AF2 (45mA) H20 G20 + C84 0.022U_0402_16V7K +1.5VS_MPLL VCCA_MPLL VCCA_TVBG VSSA_TVBG C92 0.1U_0402_16V4Z +2.5VS 2 330U_D2E_2.5VM C107 0.1U_0402_16V4Z A38 (10mA) B39 C687 +2.5VS L8 MBK1608301YZF_0603 1 C105 0.022U_0402_16V7K VCCA_LVDS VSSA_LVDS VCCHV0 VCCHV1 VCCHV2 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40 +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL VCCD_TVDAC VCCDQ_TVDAC +2.5VS_CRTDAC B26 (50mA) C39 (50mA) AF1 (45mA) VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 E21 (70mA) F21 G21 + +1.5VS C631 10U_0805_10V4Z +1.5VS_3GPLL +2.5VS (2mA) VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCD_HMPLL0 VCCD_HMPLL1 1 L45 MBK1608301YZF_0603 +1.5VS C638 0.1U_0402_16V4Z MCH_D2 C633 0.22U_0603_16V7K 2 C739 220U_D2_2VMR15 + C636 10U_0805_10V4Z 1 C632 0.47U_0603_16V4Z MCH_AB1 C630 0.22U_0603_16V7K B P O W E R C637 0.1U_0402_16V4Z C643 0.47U_0603_16V4Z MCH_A6 VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC2 (1500mA) +1.5VS C180 0.1U_0402_16V4Z AC33 G41 H41 R580 0_0805_5% C109 0.1U_0402_16V4Z VCCA_3GPLL VCCA_3GBG VSSA_3GBG +1.5VS_PCIE W=60 mils C195 0.01U_0402_16V7K AB41 AJ41 L41 N41 R41 V41 Y41 C108 0.022U_0402_16V7K C67 2.2U_0805_10V6K C627 4.7U_0805_10V4Z C VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 +2.5VS +1.5VS_DPLLB L46 MBK1608301YZF_0603 1 C117 0.1U_0402_16V4Z (60mA) B30 C30 A30 C106 0.1U_0402_16V4Z VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 H22 C118 0.022U_0402_16V7K 220U_D2_2VMR15 + VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51 VTT52 VTT53 VTT54 VTT55 VTT56 VTT57 VTT58 VTT59 VTT60 VTT61 VTT62 VTT63 VTT64 VTT65 VTT66 VTT67 VTT68 VTT69 VTT70 VTT71 VTT72 VTT73 VTT74 VTT75 VTT76 C127 10U_0805_10V4Z C629 VCC_SYNC AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1 C111 0.1U_0402_16V4Z +1.05VS (800mA) D +1.5VS_DPLLA U40H C68 0.1U_0402_16V4Z D +1.5VS A CALISTOGA_FCBGA1466~D PM@ 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Calistoga (4/6) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 of 59 Strap Pin Table CFG[3:17] have internal pull up m o c e u l b p o t p a l w W w C41 220U_D2_2VMR15 + + C40 @ 220U_D2_2VMR15 B +1.05VS M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16 VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17 +1.8V VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110 VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 MCH_AV1 AJ1 MCH_AJ1 CALISTOGA_FCBGA1466~D PM@ 2 Place near pin AV1 & AJ1 CFG[19:18] have internal pull down MCH_AT41 MCH_AM41 011 001 CFG[2:0] C717 0.47U_0603_16V4Z C718 0.47U_0603_16V4Z CFG5 CFG7 = Reserved = Mobile Yonah CPU*(Default) CFG9 = Lane Reversal Enable = Normal Operation*(Default) CFG11 = Reserved Place near pin AT41 & AM41 2 C129 0.1U_0402_16V4Z C86 0.1U_0402_16V4Z 1 = Calistoga 00 01 10 11 CFG[13:12] = 667MT/s FSB = 533MT/s FSB = DMI x = DMI x *(Default) PSB 4X CLK Enable C121 0.1U_0402_16V4Z AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 C75 0.1U_0402_16V4Z P O W E R VCC_SM0 VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4 VCC_SM5 VCC_SM6 VCC_SM7 VCC_SM8 VCC_SM9 VCC_SM10 VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15 VCC_SM16 VCC_SM17 VCC_SM18 VCC_SM19 VCC_SM20 VCC_SM21 VCC_SM22 VCC_SM23 VCC_SM24 VCC_SM25 VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36 VCC_SM37 VCC_SM38 VCC_SM39 VCC_SM40 VCC_SM41 VCC_SM42 VCC_SM43 VCC_SM44 VCC_SM45 VCC_SM46 VCC_SM47 VCC_SM48 VCC_SM49 VCC_SM50 VCC_SM51 VCC_SM52 VCC_SM53 VCC_SM54 VCC_SM55 VCC_SM56 VCC_SM57 VCC_SM58 VCC_SM59 VCC_SM60 VCC_SM61 VCC_SM62 VCC_SM63 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99 = = = = D * Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation *(Default) CFG16 = Dynamic ODT Disabled = Dynamic ODT Enabled *(Default) CFG18 = 1.05V = 1.5V CFG19 = Normal Operation * (Default) = DMI Lane Reversal Enable *(Default) = No SDVO Device Present * (Default) SDVO_CTRLDATA = SDVO Device Present CFG20 (PCIE/SDVO select) = Only PCIE or SDVO is operational *(Default) = PCIE/SDVO are operating simu C CFG5 CFG7 CFG9 Place near pin BA23 C719 10U_0805_10V4Z C VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 C679 0.47U_0603_16V4Z AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 C720 10U_0805_10V4Z AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 +1.8V U40G 2005/09/20 CFG12 1 CFG13 + C735 CFG11 CFG16 330U_D2E_2.5VM_R9 R58 @ 2.2K_0402_5% R81 @ 2.2K_0402_5% R67 @ 2.2K_0402_5% R57 @ 2.2K_0402_5% R59 @ 2.2K_0402_5% R69 @ 2.2K_0402_5% R68 @ 2.2K_0402_5% R92 @ 1K_0402_5% R95 @ 1K_0402_5% R118 @ 1K_0402_5% +3VS C650 0.47U_0603_16V4Z 2 VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57 C634 0.47U_0603_16V4Z 1 VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 P O W E R C640 0.22U_0603_16V7K C43 1U_0603_10V4Z C44 10U_0805_10V4Z C45 10U_0805_10V4Z C639 0.22U_0603_16V7K D C42 0.22U_0603_16V7K (3500mA) AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 +1.05VS +1.5VS U40F C635 0.47U_0603_16V4Z +1.05VS CFG18 CFG19 CFG20 B Place near pin BA15 CALISTOGA_FCBGA1466~D PM@ A A 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Calistoga (5/6) Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 10 of 59 A B C D E JP12 m o c e u l b p o t p a l w W w SPKL+ SPKLSPKR+ SPKR- +5VAMP R462 R464 R466 R469 20mil R458 1 1 2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% SPK_L+ SPK_LSPK_R+ SPK_R- ACES_85204-0400 Speaker Conn VOL_AMP 2 1U_0603_10V4Z 1U_0603_10V4Z 47 BYPASS R792 @ 1K_0402_5% VOLMAX 13 SE/BTL# BYPASS 20mil LOUT- SPKL- 16 SPKR- LOUT+ 11 SPKL+ ROUT+ 14 SPKR+ GND GND 12 LINRIN- BYPASS EC_MUTE ROUT- VOLUME AMP_LEFT_C AMP_RIGHT_C NBA_PLUG 44,47 NBA_PLUG EC_MUTE 40,47 SPDIF_PLUG# Q22 SI2301BDS_SOT23 D SPDIF_PLUG# G Q21 2N7002_SOT23 S +5VSPDIF 20mil APA2068KAI-TRL_SOP16 MUTE SHUTDOWN# R698 100K_0402_5% C886 4.7U_0805_10V4Z R791 @ 1K_0402_5% C566 C568 VOLMAX 0_0402_5% NBA_PLUG AMP_RIGHT_C-1 C928 0.47U_0603_16V4Z 44,45 AMP_RIGHT C927 0.47U_0603_16V4Z AMP_LEFT_C-1 2 R690 VDD VDD +5VAMP R468 100K_0402_5% 1 0.1U_0402_16V4Z 10 15 +5VAMP R467 100K_0402_5% U56 C882 44,45 AMP_LEFT C892 4.7U_0805_10V4Z 2 1 2 C881 0.1U_0402_16V4Z 1 1 S R457 1.5K_0402_1% +5VAMP W=40mil D D +5VAMP S R455 @ 5.1K_0402_1% SPDIF_PLUG# Q20 G 2N7002_SOT23 @ VOL_AMP (0.65V -> 10dB ) G 10K_0402_5% C563 330P_0402_50V7K HPF Fc = 338Hz 1 C562 S/PDIF Out JACK 330P_0402_50V7K JP40 C891 SPKR+ C888 + SPKL+ + 2005/09/05 HPOUT_L_1 150U_D_6.3VM HPOUT_R_1 150U_D_6.3VM HPOUT_L_2 47_0603_5% HPOUT_R_2 47_0603_5% R702 R699 R795 @ 1K_0402_5% 10 SPDIF 2 SPDIF 44 SPDIF +5VSPDIF 1 +5VAMP R794 @ 1K_0402_5% HPOUT_L_3 FBM-11-160808-700T_0603 HPOUT_R_3 FBM-11-160808-700T_0603 SPDIF_PLUG# R456 100K_0402_5% L51 L50 ACES_20234-0101 GRA@ C879 100P_0402_50V8J @ LINE-IN JACK JP41 44 LINE_R 44 LINE_L LINE_R LINE_L L48 FBM-11-160808-700T_0603 L49 FBM-11-160808-700T_0603 C885 220P_0402_50V7K LINE_R_R 3 LINE_L_R SUYIN_010164FR006G118ZL GRA@ C884 220P_0402_50V7K DSP_ENABLE# MIC1_VREFO_R R775 2.2K_0402_5% INT_MIC_L 45 45 MIC1_DSP_P 2005/09/06 15mil ACES_85204-0200 R741 0_0402_5% INTMIC@ INT_MIC_L MIC1_DSP_N 45 44 MIC1_R 44 MIC1_L FBM-11-160808-700T_0603 L54 L35 C569 220P_0402_50V7K MIC1_R_1 MIC1_L_1 FBM-11-160808-700T_0603 JP42 R776 2.2K_0402_5% JP13 2005/09/09 Int MIC Conn DSP_ENABLE# 45 MIC JACK 1 MIC1_VREFO_L C876 220P_0402_50V7K 10 11 12 13 14 15 16 HPOUT_R_3 1 JP44 INT_MIC_L MIC1_L_1 MIC1_R_1 LINE_R_R LINE_L_R HPOUT_L_3 DSP_ENABLE# SPDIF_PLUG# +5VSPDIF SUYIN_010164FR006G118ZL GRA@ SPDIF 40,42 RCIRRX +3VALW 2 10 11 12 13 14 15 16 ACES_87213-1600G GEN@ 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Amplifier & Audio Jack Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 E 46 of 59 A B C D m o c e u l b p o t p a l w W w E +5VAMP R459 100K_0402_5% SUB@ + - 1U_0603_10V4Z SUB@ +5VAMP R701 10K_0402_5% SUB@ + - P 0.1U_0402_16V4Z SUB@ C564 U57A TLV2462CDR_SO8 R700 SUB@ O 1K_0402_5% SUB@ 0.68U_0603_10V6K O G 2 1U_0603_10V4Z SUB@ P C560 C889 SUB@ 44 MONO_OUT G C565 SUB@ 1U_0603_10V4Z C567 0_0402_5% SUB@ R461 43K_0402_5% SUB@ C570 SUB@ 0.47U_0603_16V4Z BYPASS R460 46 BYPASS C890 U57B TLV2462CDR_SO8 SUB@ MIX_OUT 0.22U_0603_16V7K SUB@ 10mil BYPASS 2 10mil fo= 725 Hz Fc(high)= 33.8Hz 10K_0402_5% SUB@ D G 40,46 EC_MUTE S 44,46 NBA_PLUG D G Q23 2N7002_SOT23 SUB@ 3 S Q24 2N7002_SOT23 SUB@ C880 SUB@ 0.1U_0402_16V4Z IN VO- SD# GND VDD SE/BTL# BYPASS VO+ 0.47U_0603_16V4Z JP20 ACES_85204-0200 SUB@ WOOFER+ TPA0211DGN_MSOP8 C878 SUB@ SUB@ 30mil WOOFER- 1 R694 40 MUTE_WOOFER# U55 WOOFER_IN R691 SUB@ 100K_0402_5% R697 20K_0402_5% SUB@ MIX_OUT MUTEWOOFER# +5VAMP 4 Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Issued Date Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Subwoofer Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Friday, November 11, 2005 Sheet E 47 of 59 H3 H_C236D162 @ H2 H_S366D138 @ H5 H_C197D197N @ @ 1 FAN1 Conn H4 H_S315D138 H1 H_S394D138 m o c e u l b p o t p a l w W w @ +5VS +5VS 10U_1206_16V4Z H7 H_TC236BC165D165 H9 H_TC236BC165D165 H10 H_TC236BC165D165 H6 H_C236D162 R45 10K_0402_5% 1 @ H19 H_TC177BC144D144 @ H20 H_C158D158N @ H21 H_S394X374D138 @ H24 H_S354X293D138 @ @ @ @ 2005/09/20 ACES_85205-03001 H12 H_O87X68D47X28 @ 1 H18 H_O87X68D47X28 @ H27 H_S315D138 @ @ H26 H_O217X157D217X157N H17 H_O87X68D47X28 @ H25 H_S374X354D138 @ @ H11 H_O87X68D47X28 @ 1 H28 H_S354X335D138 H29 H_C236D162 C59 1000P_0402_50V7K @ +VCC_FAN1 40 FAN_SPEED1 H16 H_TC177BC144D144 @ JP19 40mil @ 1 C58 1000P_0402_50V7K @ H13 H23 H22 H_S374X354D138 H_TS559X295BS394X276D138 H_S394D138 +3VS H15 H_S394D138 @ H14 H_S394D138 C51 10U_1206_16V4Z @ G993P1UF_SOP8 @ D5 1N4148_SOT23 GND GND GND GND VEN VIN VO VSET 2 +VCC_FAN1 EN_DFAN1 40 EN_DFAN1 H8 H_TC236BC165D165 D4 1SS355_SOD323 U2 1 C47 @ FAN2 Conn +5VS +5VS C344 1000P_0402_50V7K JP25 CF13 @ CF9 CF1 @ CF2 @ CF6 @ CF3 @ CF15 @ CF5 @ CF4 @ CF12 @ 1 CF10 @ 1 CF7 @ CF11 @ @ 1 CF19 @ @ CF21 CF16 @ @ 1 +VCC_FAN2 40 FAN_SPEED2 @ CF8 40mil @ CF18 1 CF17 R207 10K_0402_5% @ FD6 @ 1 C343 1000P_0402_50V7K CF14 FD4 @ +3VS @ CF20 C339 10U_1206_16V4Z FD5 @ G993P1UF_SOP8 D9 1N4148_SOT23 FD3 @ GND GND GND GND VEN VIN VO VSET 2 40 EN_DFAN2 +VCC_FAN2 EN_DFAN2 FD1 @ FD2 D8 1SS355_SOD323 U10 10U_1206_16V4Z C338 @ ACES_85204-0300 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FAN & Screw Hole Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Friday, November 11, 2005 Sheet 48 of 59 A B C D E +5VALW m o c e u l b p o t p a l w W w R294 100K_0402_5% +5VALW +5VS SYSON 37,40,55 SYSON C464 SI4800BDY_SO8 C465 R358 470_0603_5% 10U_0805_10V4Z 2 1U_0603_10V4Z AOS 4422 10U_0805_10V4Z 2 10U_0805_10V4Z R295 100K_0402_5% 2 S S S G Q8 2N7002_SOT23 C419 D D D D S C418 D G U16 1 SYSON# +5VALW TO +5VS D 5VS_GATE SUSP G Q12 2N7002_SOT23 S R317 200K_0402_5% +VSB D S C455 0.1U_0603_25V7K +5VALW 2 Q11G 2N7002_SOT23 SUSP R362 100K_0402_5% SUSP D 43,53,54 SUSP S Q13 2N7002_SOT23 G 37,40,41,43,54 SUSP# R363 100K_0402_5% +3VALW TO +3VS +1.8V to +1.8VS +3VALW +1.8V +3VS +1.8VS SI4800BDY_SO8 10U_0805_10V4Z AOS 2 10U_0805_10V4Z 4422 C518 R423 470_0603_5% 10U_0805_10V4Z 2 1U_0603_10V4Z S 10U_0805_10V4Z 2 10U_0805_10V4Z C755 C756 R590 470_0603_5% 10U_0805_10V4Z 2 1U_0603_10V4Z AOS 4422 D SUSP G Q17 2N7002_SOT23 1.8VS_GATE R586 510K_0402_5% +VSB SUSP S 1 5VS_GATE C740 S S S G SI4800BDY_SO8 D C741 D D D D 1 C514 C509 S S S G D D D D 1 C508 U44 U27 D G 2 SUSP G Q33 2N7002_SOT23 C746 0.1U_0603_25V7K 2 S 1 R583 470_0603_5% @ 1 1 S D SUSP G Q29 2N7002_SOT23 R123 470_0603_5% @ D SUSP G Q2 2N7002_SOT23 @ S D SUSP G Q3 2N7002_SOT23 @ S S R43 470_0603_5% @ D SUSP G Q7 2N7002_SOT23 +1.8V R497 470_0603_5% 1 D SUSP G Q10 2N7002_SOT23 +VGA_CORE 3 R238 470_0603_5% D +0.9VS 2005/09/04 2 1 R290 470_0603_5% S +1.05VS 2005/09/04 +2.5VS 2005/09/04 +1.5VS Q31 S 2N7002_SOT23 SYSON# G Q32 2N7002_SOT23 @ 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title DC Interface Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 E 49 of 59 B PR3 1K_1206_5% PD2 RLZ24B_LL34 1 PR7 1K_1206_5% PR5 PR6 1K_1206_5% 470K_0402_5% PR4 1N4148_SOD80 B+ PQ1 TP0610K-T1-E3_SOT23 1 1 PR8 470K_0402_5% PQ2 DTC115EUA_SC70 40,52 ACOFF PQ3 DTC115EUA_SC70 3 560P_0402_50V7K PC4 12P_0402_50V8J PC3 12P_0402_50V8J PC2 2 560P_0402_50V7K PC1 PR2 10_1206_5% SINGA_2DC-G756I200 PR1 1K_1206_5% PD1 VIN 1 G G VIN FBMA-L18-453215-900LMA90T_1812 D m o c e u l b p o t p a l w W w PL2 ADPIN PCN1 C 470K_0402_5% A 2 VIN BATT+ PD4 1N4148_SOD80 PD3 RB751V-40TE17_SOD323-2 PR9 33_1206_5% VL PQ4 TP0610K-T1-E3_SOT23 1 VS LM393DR_SO8 PU1A PC11 GND PC10 1U_0805_25V4Z ACIN PR19 560_0402_5% 560_0402_5% CHGRTC Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR20 34K_0402_1% RTCVREF 2005/06/20 PC7 0.01U_0402_25V7Z PR21 47K_0402_5% PACIN 52,54 PQ6 DTC115EUA_SC70 PR22 @ 66.5K_0402_1% +5VALWP Deciphered Date Compal Electronics, Inc 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B G Compal Secret Data Security Classification A RHU002N06_SOT323 PQ5 S BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V Issued Date D 3 OUT 4.7U_0805_6.3V6K IN 2 3.3V PR18 PR16 499K_0402_1% PU2 G920AT24U_SOT89 PR15 191K_0402_1% PC8 0.1U_0402_16V7K RTCVREF PR17 200_0603_5% 3 - 2 RB715F_SOT323 + O PRG++ 1 52 ACON PC9 1000P_0402_50V7K PD5 P 27,51,53 MAINPWON PR13 100K_0402_1% PR11 499K_0402_1% G VS PC6 0.1U_0603_25V4Z 42,43 51ON# PR14 22K_0402_5% 2 PR12 100K_0402_5% 0.22U_1206_25V7K PC5 1 CHGRTCP B+ PR10 2.2M_0402_5% C Title DCIN/DECTOR/RTC Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 D Sheet 50 of 59 C m o c e u l b p o t p a l w W w PC12 0.1U_0603_25V7K 2 5HG PR23 0_0402_5% PC13 0.1U_0603_25V7K BST3B_3V PD6 CHP202UPT_SOT323-3 MAX8734A_B+ 3HG VL PL3 FBMA-L11-322513-151LMA50T_1210 BST5B_5V B+ D 1 B A 1 PC18 4.7U_1206_25V6K 2 +3VALWP SPOK 53 + PC25 150U_D_6.3VM PR37 0_0402_5% 2 PR39 100K_0402_1% 1 PC29 0.047U_0402_16V7-K ILM5 PR43 499K_0402_1% PR38 100K_0402_1% PR42 ILM3 499K_0402_1% 25 23 10 PR40 0_0402_5% 1 2VREF_1999 PR41 47K_0402_5% PC28 1U_0603_6.3V6M 2 1 PC27 4.7U_0805_10V6K 27,50,53 MAINPWON 2VREF_1999 PC26 0.22U_0603_10V7K PR36 0_0402_5% PL5 10U_LF919AS-100M-P3_4.5A_20% PR29 0_0402_5% BST3A DH3 DL3 LX3 ILM5 28 26 24 27 22 PC17 2200P_0402_50V7K PR27 47_0402_5% 11 AO4916L_SO8 PR33 @ 3.57K_0402_1% REF ILM3 D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K LDO3 0_0402_5% PR34 PRO# LX5 DL5 ILIM5 OUT5 PU3 FB5 BST3 N.C.MAX8734AEEI+_QSOP28 DH3 DL3 SHDN# LX3 ON5 OUT3 ON3 FB3 SKIP# PGOOD PC21 1U_0805_16V7K 2 17 13 TON VCC 18 20 V+ 15 19 21 12 LD05 LX5 DL5 GND DH5 PC24 0.047U_0402_16V7-K ILIM3 16 PR28 0_0402_5% PR35 0_0402_5% 2 PZD1 RLZ5.1B_LL34 BST5 DH5 PR31 47K_0402_5% 2 PR32 100K_0402_5% PR30 10.2K_0402_1% VS @ PC23 150U_D_6.3VM + PC22 4.7U_0805_6.3V6K PL4 10U_LF919AS-100M-P3_4.5A_20% BST5A_5V 14 +5VALWP 1 1U_1206_25V7K PC19 AO4916L_SO8 VL PQ8 PC14 0.1U_0603_25V7K DL5 MAX8734A_B+ PR26 0_0402_5% PC20 0.1U_0603_25V7K G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A PC16 4.7U_1206_25V6K PC15 2200P_0402_50V7K 2 PQ7 MAX8734A_B+ PR24 4.7_1206_5% MAX8734A_B+ +5VALWP Ipeak = 6.66A ~ 10A +3VALWP Ipeak = 6.66A ~ 10A 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +5VALWP/+3VALWP Size Document Number Custom Date: Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 D Sheet 51 of 59 A B C D E Charger Iadp=0~4.74A(90W) charger_DHI LX 23 charger_LX DLO 21 charger_DLO BST 24 charger_BST DLOV 22 charger_DLOV BATT+ 19 18 16 G S S S PR49 10K_0402_1% 2 PR203 33_1206_5% 14 20 PGND GND CCS PC154 1U_0603_10V6K PC48 4.7U_1206_25V6K CSIP CSIN BATT PD14 1SS355_SOD323 PC47 4.7U_1206_25V6K 2 PC46 4.7U_1206_25V6K LDO PC155 1U_0805_25V4Z MAX1908-CCS PC157 0.01U_0402_25V7K 50 ACON PR202 0_0402_5% 1908LDO CCI 1 PR64 22K_0402_5% PR61 0.015_2512_1% 10U_LF919AS-100M-P3_4.5A_20% IINP CCV PL7 28 ACOK# SHDN# ACIN ICHG PC152 0.1U_0603_25V7K VCTL ICTL 11 10 1N4148_SOD80 2 2 PR205 100K_0402_1% 15 13 PR206 1K_0402_1% 24.9K_0402_1% PR204 REFIN PR200 15K_0402_1% 40 IREF PC150 @ 1000P_0402_50V7K 12 1 ACOFF 40,50 25 ACOFF DHI 2 PQ41 SI4810BDY-T1-E3_SO8 CLS PC156 0.01U_0402_25V7K PR199 9.31K_0402_1% ACOFF# PQ15 SI4810BDY-T1-E3_SO8 D D D D G S S S 26 REF VIN 2 CSSN CELLS 1 27 2 PR201 100K_0402_1% 1 PC151 0.1U_0402_16V7K PQ17 RHU002N06_SOT323 CSSP D D D D 2 D S DCIN PR47 47K_0402_1% PQ13 DTC115EUA_SC70 PU4 MAX1908ETI_QFN28 1908LDO PD8 50,54 PACIN 17 PR197 @ 0_0402_5% G ACOFF# 1 PQ42 SI2301DS_SOT23~D 57.6K_0402_1% PR198 PR55 150K_0402_5% S RHU002N06_SOT323 PQ16 G D PQ14 DTC115EUA_SC70 S 3 BATT+ 1 PQ43 2 PR211 10K_0402_5% RHU002N06_SOT323 D PR71 200K_0402_1% G S D PC50 0.01U_0402_25V7Z - LM358ADR_SO8 P G - S 4 PU5A + PR210 511K_0402_1% 40 BATT_OVP PU5B + VS G +3VALWP PR68 300K_0603_0.1% P IREF=0.73~3.3V PR67 845K_0603_1% IREF=0.832*Icharge 4S CC-CV MODE : 16.8V BATT-OVP=0.111*BATT+ 2P4S:4800mAH/cell 0.8C=3.84A BATT+ 1 PC159 0.1U_0402_16V7K 2 PR208 100K_0402_5% LI-4S :17.8V BATT-OVP=1.9758V Charge voltage VS PR209 10K_0402_5% 40 FSTCHG PC158 0.1U_0402_16V7K PR207 0_0402_5% PC49 0.01U_0402_25V7Z PC32 0.1U_0603_25V7K 1 53 6C/8C# G PC148 1U_0603_10V6K D PC33 2200P_0402_50V7K 2 PD13 VIN 47K 1 1SS355_SOD323 PC149 0.1U_0603_25V7K PC147 0.1U_0603_25V7K PC153 0.01U_0402_25V7K 2 PQ12 DTA144EUA_SC70 47K PR45 200K_0402_1% PQ11 AO4407L_SO8~N 3 PR46 47K_0402_5% PC34 0.1U_0603_25V7K 1 PC146 0.1U_0603_25V7K CHG_B+ PL6 FBMA-L18-453215-900LMA90T_1812 PC30 4.7U_1206_25V6K 1 0.01_2512_1% 4 B+ PR44 P3 VIN PQ10 AO4407L_SO8~N PC31 4.7U_1206_25V6K m o c e u l b p o t p a l w W w P2 PQ9 AO4407L_SO8~N LM358ADR_SO8 6C/8C# 53 G RHU002N06_SOT323 PQ44 OVP voltage : LI-3S :17.8V BATT-OVP=1.9758V BATT-OVP=0.111*BATT+ 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Charger Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Sheet Friday, November 11, 2005 E 52 of 59 A B C D PR212 100K_0402_5% 6C/8C# 52 BATT++ VL 1 EC_SMB_DA1 15,40,41,45 PR90 100_0402_5% EC_SMB_CK1 15,40,41,45 + - PU1B PR80 150K_0402_1% MAINPWON 27,50,51 O LM393DR_SO8 PR86 VL 150K_0402_1% PR88 150K_0402_1% 2 PR89 100_0402_5% PC57 1U_0805_25V4Z +3VALWP PC56 1000P_0402_50V7K PR87 6.49K_0402_1% 2 BATT_TEMP 40 SUYIN_200275MR007G161ZL PJP1 TM_REF1 100K_0603_1%_TH11-4H104FT PH1 PR85 1K_0402_5% BATT_TEMP 61.9K_0402_1% PR83 P PR84 1K_0402_5% 1 VL VS PR81 10.7K_0402_1% SM ART Batter y: GND SMC 3.SMD 4.TS B/I ID BA TT+ PR214 @1K_0402_5% 2 PC54 1000P_0402_50V7K PC53 0.01U_0402_25V7Z PR77 442K_0603_1% PR213 1K_0402_5% 1 FBMA-L18-453215-900LMA90T_1812 +3VALWP PC55 0.1U_0603_25V7K 2 G BATT+ PL8 PJP2 battery connector BATT++ 1 PH1 under CPU botten side : CPU thermal protection at 80 degree C Recovery at 44(45) degree C m o c e u l b p o t p a l w W w BATT+ +1.8V PU6 PR91 1K_0402_1% NC NC TP PC65 @ 0.1U_0402_16V7K PQ22 VOUT PC59 1U_0603_6.3V6M 2 +0.9VSP PC63 22U_1206_6.3V6M S PC62 0.1U_0402_16V7K D G S VREF @ PC64 22U_1206_6.3V6M PQ21 RHU002N06_SOT323 RHU002N06_SOT323 +3VALW D G 0_0402_5% SUSP 43,49,54 SUSP PC66 @ 0.1U_0402_16V7K PR93 1K_0402_1% 2 PR95 PR94 22K_0402_5% PR97 0_0402_5% NC APL5331KAC-TRL_SO8 PC61 0.1U_0603_25V7K 2 PC60 0.22U_1206_25V7K VL 51 SPOK VCNTL GND 1 PR92 100K_0402_5% PR96 100K_0402_5% VIN 2 +VSBP PC58 10U_1206_6.3V7K B+ 1 PQ20 TP0610K-T1-E3_SOT23 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP/+0.9VSP Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 D Sheet 53 of 59 AC Adapter Detector m o c e u l b p o t p a l w W w PJ2 PAD-OPEN 3x3m (2.5A,100mils ,Via NO.=5) PAD-OPEN 3x3m + - 2 +VSB JUMP_43X79 PC52 1000P_0402_50V7K PU7A O AC IN ACIN 28,40 PACIN LM393DR_SO8 PC51 0.1U_0603_25V7K PR98 10K_0402_5% PZD2 RLZ4.3B_LL34 PACIN 50,52 PR99 10K_0402_5% +VSBP +1.05VS PAD-OPEN 3x3m PR72 20K_0402_1% PJ8 PR74 22K_0402_5% (0.3A,40mils ,Via NO.= 2) PJ7 PR73 10K_0402_5% 1 +2.5VS PAD-OPEN 3x3m (4.5A,180mils ,Via NO.= 9) VIN VS +2.5VSP +3VALW 1M_0402_1% PR69 84.5K_0402_1% PJ6 VIN (0.3A,40mils ,Via NO.= 2) PJ5 +1.05VSP +0.9VS PAD-OPEN 3x3m (5A,200mils ,Via NO.= 10) PR75 P +0.9VSP G +5VALW PAD-OPEN 3x3m +3VALWP D PJ4 +5VALWP Vin Detector 17.90V/17.24V (6A,240mils ,Via NO.= 12) PJ3 +1.8V D PAD-OPEN 3x3m 1 +1.8VP +1.5VS 2 PJ1 +1.5VSP (2A,80mils ,Via NO.= 4) - PU7B P + G O LM393DR_SO8 SUSP# 37,40,41,43,49 PC72 @ 1U_0805_25V4Z BST PR112 4.7_1206_5% PR113 7.15K_0402_1% +1.5VSP PR116 1.5K_0402_1% PR114 30_0402_5% + 2 PC83 680P_0603_50V8J 1SS355_SOD323 PC78 0.1U_0603_25V7K VFB AGND 7AGND VTT VCCA VTT REFEN +5VALW B PC79 22U_1206_6.3V6M PR111 200K_0402_1% 2 PC84 0.033U_0603_25V7K RTCVREF PR115 64.9K_0402_1% PC82 0.047U_0402_16V4Z 1 PR117 825_0402_1% PGND PL10 3.0UH_SPC-07040-3R0GP_5A_30% 2 PC80 330U_D2E_2.5VM 1 1 4.7_0402_5% PR109 VIN REF_EN PD9 1.5V_DL2 2 4.7U_0805_6.3V6K 1 1.5V_BST PC76 +2.5VSP AO4916L_SO8 GND MAX8578EUB+T_UMAX10 +3VALW PC77 1U_0603_6.3V6M 71.5V_LX DL AGND LX VL CM8562IS_PSOP8 AGND FB PU9 G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A 1.5V_VL PQ23 1.5V_FB PR108 0_0402_5% 1.5V_DH2 10_0603_1% PR110 81.5V_DH1 0.1U_0603_25V7K PC81 DH PC75 4.7U_1206_25V6K EN SS 3300P_0402_50V7K OCSET +5VS PU8 1.5V_SS 1.5V_DL1 PC74 PC73 0.01U_0402_25V7Z 1.5V_OCSET 10 B C 1.5V_EN 2 PC71 4.7U_1206_25V6K 0_0402_5% PR106 2 PR107 4.99K_0402_1% RTCVREF PR70 10K_0402_5% PC70 0.1U_0603_25V7K B+ PL9 FBMA-L11-322513-151LMA50T_1210 MAX8578_B+ 2 C D PC85 0.1U_0603_25V7K RHU002N06_SOT323 PQ24 SUSP G SUSP 43,49,53 S A A Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Issued Date Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.5VSP/RTCVREF Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 Sheet 54 of 59 m o c e u l b p o t p a l w W w PL1 0.1U_0603_25V7K PC94 1 PC91 4.7U_1206_25V6K 2 1.8U_D104C-919AS-1R8N_9.5A_30% +1.05VSP 11 ON1 @ D D D D B FB1 + PC97 150U_D_6.3VM 15 14 12 4.7U_0805_6.3V6K PC99 OUT2 FB2 ON2 PR121 499_0402_1% CS1 OUT1 BST2 DH2 LX2 DL2 MAX8743EEI_QSOP28 CS2 28 @ LX1 DL1 G S S S 27 24 BST2A_1.05V DH_1.05V LX_1.05V DL_1.05V DH1 LX_1.8V DL_1.8V 19 18 17 20 16 PQ28 SI4810BDY-T1-E3_SO8 26 21 UVP DH_1.8V PR120 0_0402_5% VDD BST1 VCC 25 B 22 PU10 BST1A_1.8V V+ G S S S 8.2K_0402_5% PR119 0_0402_5% PQ27 SI4810BDY-T1-E3_SO8 PR219 PR122 10K_0402_1% VS_ON 43 2 PR124 0_0402_5% PR128 100K_0402_1% 15K_0402_1% 13 PR125 33K_0402_1% PR126 2 PC101 0.22U_0603_10V7K ILIM2 ILIM1 PR127 100K_0402_1% REF 10 SKIP GND OVP PC100 0.01U_0402_25V7Z @ PR123 0_0402_5% PGOOD TON 23 1 2 37,40,49 SYSON PR220 10K_0402_1% PC90 4.7U_1206_25V6K G S S S PL12 0.1U_0603_25V7K PC93 2 PR118 20_0603_5% C @ BST1B_1.8V 1U_0805_25V4Z PC95 PC89 2200P_0402_50V7K G S S S PQ25 SI4800BDY-T1-E3_SO8 BST2B_1.05V D D D D + PC98 4.7U_0805_6.3V6K PC96 150U_D_6.3VM D D D D +1.8VP 0.1U_0603_25V7K PC92 PL11 1.8U_D104C-919AS-1R8N_9.5A_30% +5VALW PD10 DAP202U_SOT323 PQ26 SI4800BDY-T1-E3_SO8 B+ FBMA-L11-322513-151LMA50T_1210 D D D D MAX8743_B+ @ C D PC87 4.7U_1206_25V6K PC86 2200P_0402_50V7K D PC88 4.7U_0805_6.3V6K A A Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Issued Date Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.05VSP/+1.8VP Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 Sheet 55 of 59 +5VS m o c e u l b p o t p a l w W w CPU_B+ B+ PL13 FBMA-L11-322513-201LMA40T_1210 PR129 D2 LX1 28 LX1 CPU 34 D3 DL1 26 DL1 CPU CPU_VID4 35 D4 PGND1 27 CPU_VID5 36 D5 GND 18 CPU_VID6 37 D6 CSP1 17 TIME CSN1 16 CSN1_CPU FB_CPU FB 11 REF CCI 10 C CI_CPU DPRSLPVR DH2 21 DH2_CPU BST2 20 BST2_CPU LX2 22 LX2_CPU DL2 24 DL2 CPU PGND2 23 DPRSTP PSI PWRGD CLKEN 15 CSN2 CPU GNDS 13 PR152 @ 1K_0402_1% PR156 3.65K_0402_1% PC116 VSSSENSE PR162 20K_0402_1% PQ32 SI7840DP_SO8 0_0402_5% 1 PC108 2200P_0402_50V7K PC107 0.1U_0603_25V7K 2 PC118 470P_0402_50V8J PR216 PR169 @ 10_0402_5% 2 CPU_B+ B PR170 4.7_1206_5% 1 PC127 680P_0402_50V7-K PQ33 IRF8113PBF_SO8 3 DL2 CPU @ PR171 2.1K_0402_1% IRF8113PBF_SO8 PQ34 PL15 P_0.36H_ETQP4LR36WFC_24A_20% PC126 0.1U_0402_16V7K PR168 10K_0402_5% 40 POUT @ 100_0402_5% PC117 4700P_0402_25V7K PR160 3K_0603_1% PR157 PC122 10U_1206_25VAK VSSSENSE PC121 10U_1206_25VAK 2 PR167 @ 0_0402_5% 1 36,40 TV_THERM# PR165 100_0402_5% VRHOT PR166 56_0402_5% B BSTM2_CPU +3VS PR164 @ 10K_0402_5% @ 1000P_0402_50V7K CPU_VCC_SENSE PC119 1000P_0402_50V7K PR163 0_0402_5% MAX8770GTL+_TQFN40 NTC PR159 @ 3K_0603_1% PC120 POUT PC106 10U_1206_25VAK PR194 0_0402_5% 14 CSN2 PR153 CSP2 VRHOT SHDN 1 PC105 10U_1206_25VAK PR151 0_0402_5% 2 0_0402_5% PR161 2 40 VR_ON 1 14 CLK_ENABLE# CSP2_CPU 6,14,28 VGATE 38 PR155 @ 2K_0402_1% C @ 2 PR154 @ 2K_0402_1% PR158 0_0402_5% 0.22U_0603_16V7K PC114 40 @ 10KB_0603_1%_TH11-3H103FT PC125 2200P_0402_50V7K 2 3.48K_0402_1% NTC PH3 PR145 2 PC124 0.1U_0603_25V7K 1 +CPU_CORE PC123 10U_1206_25VAK 0.22U_0603_16V7K 39 IRF8113PBF_SO8 0_0402_5% CCV 12 PQ30 PSI# +3VS PC113 @ CSP1 CPU 0.22U_0603_16V7K PR150 4,27 H_DPRSTP# PC115 71.5K_0402_1% +CPU_CORE PL14 P_0.36H_ETQP4LR36WFC_24A_20% 2 33 PR215 VCCSENSE D 10_0402_5% CPU_VID3 PC102 100U_25V_M PR144 CPU_VID2 29 30 DH1 + PR139 4.7_1206_5% BST1 D1 0_0402_5% D0 32 0.22U_0603_16V7K PC111 BSTM1_CPU 31 6,28 PM_DPRSLPVR 499_0402_1% PC104 10U_1206_25VAK 1 470P_0402_50V8J 0_0402_5% 200K_0402_5% PR131 1 CPU_VID1 C PR149 PR135 CPU_VID0 PR1472 PR148 0_0402_5% BST1_CPU PC112 680P_0402_50V7-K 2.1K_0402_1% PR141 PR143 0_0402_5% PQ31 IRF8113PBF_SO8 PR142 0_0402_5% 25 TON PR140 0_0402_5% VDD THRM DL1 CPU PR138 0_0402_5% Vcc PR137 0_0402_5% PR136 0_0402_5% 19 0_0402_5% PR134 0_0402_5% V CC PQ29 SI7840DP_SO8 PU11 NTC PH2 100K_0603_1%_TH11-4H104FT 2 PR132 13K_0402_1% 2 PC109 2.2U_0603_6.3V6K PC110 1U_0603_6.3V6M D 0_1206_5% PR130 10_0402_5% PC103 0.01U_0402_25V7Z 5VS12 NTC PR172 3.48K_0402_1% PH4 10KB_0603_1%_TH11-3H103FT @ PR174 0_0402_5% A 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0.22U_0603_16V7K A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date PC128 Title +CPU_CORE Size Document Number Custom Date: R ev 0.2 HBL50 LA-2921P Friday, November 11, 2005 Sheet 56 of 59 PL18 +5VALW C +1.2VSP PC129 2200P_0402_50V7K 1 4.7U_0805_6.3V6K PC142 2 @ FB_1.2V VGA_ON PR184 0_0402_5% REF_VGA VGA_ON 43 VDD_PWRGOOD 17 PR182 49.9K_0402_1% PR195 @ 0_0402_5% 13 PR188 205K_0402_1% B PR189 15K_0402_1% PR192 100K_0402_1% PR191 200K_0402_1% 10 1REF_VGA 2 PC144 0.22U_0603_10V7K S PQ39 @ RHU002N06_SOT323 LX_1.2V DL_1.2V + 15 14 12 DH_1.2V OUT2 FB2 ON2 BST1A_1.2V PR178 10K_0402_1% 19 18 17 20 16 PC139 150U_D_6.3VM BST2 DH2 LX2 DL2 CS2 REF SKIP OVP REF_VGA D 21 MAX8743EEI_QSOP28 PGOOD TON ON1 ILIM2 ILIM1 @ 100K_0402_1% 22 FB1 11 UVP CS1 OUT1 VDD S +1.2VSP PL16 3.0UH_SPC-07040-3R0GP_5A_30% 28 1 D PR193 @ 100K_0402_5% 1 G PC145 @ 0.01U_0402_25V7Z 0.1U_0603_25V7K PC136 2 LX1 DL1 VCC 27 24 V+ DH1 G 15 POWER_SEL 26 GND BST1 23 LX_VGA DL_VGA 25 PR186 210K_0402_1% 2 PR196 15K_0402_1% @ PR190 @ 100K_0402_5% DH_VGA @ AO4916L_SO8 PR177 0_0402_5% PR180 PR187 150K_0402_1% @ 1U_0805_25V4Z PR175 PC138 20_0603_5% 1 PU12 BST1A_VGA PR185 0_0402_5% +5VALW G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A BST2B_1.2V 0.1U_0603_25V7K PC137 VGA_ON @ +VGA_CORE PC131 4.7U_0805_6.3V6K PD12 DAP202U_SOT323 PC130 4.7U_1206_25V6K PQ35 FB_VGA B B+ FBMA-L11-322513-151LMA50T_1210 AO4410_SO8 +1.1V(VGA@) PR176 2_0402_5% PC160 680P_0402_50V7-K DL_VGA PQ38 PR217 @ DL_VGA 4.7_1206_5% 8 @ PR179 15K_0402_1% PQ37 AO4410_SO8 PC141 4.7U_0805_6.3V6K 2 PC140 330U_D2E_2.5VM + 0.1U_0603_25V7K PC135 1 0.56UH_ETQP4LR56WFC_21A_20% C 1 PL17 +VGA_CORE_P +1.025V D BST1B_VGA PR218 +0.95V(VGA@+G72@) VGA_B+ 0_0402_5% L +VGA_CORE FOR G72 +VGA_CORE_P H +VGA_CORE FOR G73 @ PQ36 SI7840DP_SO8 POWER_SEL 1 2 PC132 2200P_0402_50V7K PC134 4.7U_1206_25V6K m o c e u l b p o t p a l w W w PC133 4.7U_1206_25V6K D PQ40 @ RHU002N06_SOT323 PJ10 +1.2VSP +1.2VS PAD-OPEN 3x3m A A PJ9 +VGA_CORE_P +VGA_CORE +VGA_CORE_P +VGA_CORE PAD-OPEN 3x3m 2005/06/20 Issued Date PJ11 Compal Electronics, Inc Compal Secret Data Security Classification PAD-OPEN 3x3m Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +VGA_CORE_P/+1.2VSP Size B Date: Document Number Rev 0.2 HBL50 LA-2921P Friday, November 11, 2005 Sheet 57 of 59 A > B Change List Page09 : Add C49 & C887 220U_D2_4VM m o c e u l b p o t p a l w W w Page10 : No stuff R57 2.2K_0402_5% Page14 : Add R711 10K_0402_5% to set 96MHz output Change Q14 & Q15 pin1 net name to connect to ICH7M Change U19 ICS9LPRS325CKLFT part number to SA00000RE20 Page15 : Change C663, C664 from 22P_0402_50V8J to 18P_0402_50V8J Page18 : Modify VGA Device ID for G72MV & G73 Page24 : Change VGA_DDC_CLK & VGA_DDC_DATA to Q26 & Q27 Level shift Add R781 & R782 4.7K_0402_5% Change C589, C596, C583, C587, C594, C585 to 150P_0402_50V8J Page05 : No stuff C608, C614 Page12 : Change JP22 Footprint Page14 : Change R620 from 2K_0402_5% to 10K_0402_5% & add Q38 Page15 : Delete DVI pull high resistor Page17 : AddC96 330U for +VGA_CORE Page18 : Modify PEX_CFG[0 2] setting from 02 to 01 D Page30 : Delete R395 & C486, add R394 for SATA bridge reset timing Modify SATA HDD connector library Page31 : Delete IDE_CD_L, IDE_CD_R & CD_GNDA Page28 : Change SB_INT_FLASH_SEL# from ICH7M GPIO38 to GPIO33 Page34 : Add R783, R784, R785 for BCM5787M, stuff R214 when use BCM4401E, Del R168, change Q5 P/N Page29 : Change C437 from 0.1U_0402_16V4Z to 1U_0402_6.3V4Z 10 Page36 : Add +3VS, GND at JP30 for 3G device 10 Page30 : Change PATA HDD+ODD select resistor form RP to R_0402 (0_0402_5%) 11 Page38 : No stuff U14, R253, R246 & stuff R261 11 Page34 : Stuff R175 & no stuff R182( 0_0402_5%) for BCM4401E/BCM5789M/BCM5787M 12 Page40 : Reserved R793 for ALC883 pin47 EAPD, & define KB910 Pin174 as EC_PWROK 12 Page35 : Modify LAN_ACTIVITY# & LAN_LINK# LED color 13 Page41 : No stuff U21, U30, C490, R391, R390, R388 & stuff R418 13 Page 36 : Add JP38 & C895 for CAMERA Swap JP17 PCIE TX & RX Signal Swap JP30 PCIE TX & RX Signal 14 Page37 : Connect JP34 SMBus interface to ICH7M Change JP4 & JP5 USB connector to BOTTOM 14 Page42 : Modify SW9 Pin1, Pin5 as NC, no stuff C7 15 Page43 : Modify Power OK circuit add R790 for EC_PWROK, reserved Q41, R420, C512 add D35, D37, Change BATT1 P/N to SP093PA0200 16 Page44 : Delete ALC883 CD input circuit, add HD_EAPD# signal 17 Page46 : Add C927, C928, reserved R791, R792 15 Page38 : Add 1394@ BOM Structure C B > C Change List Page06 : No stuff R100 10K_0402_5% D 18 Page49 : Stuff Q33 16 Page41 : Delete LCM interface Extension I/O No stuff R390 & Stuff R418 for Flash ROM interface C 17 Page42 : Change JP11 from 34 pin to 24 pin Change SW8 & SW9 Add JP37 18 Page43 : Change U28 Part Number Change SW1 Part Number Change R425 from 10K_0402_5% to 62K_0402_1% Change R422 from 10K_0402_5% to 62K_0402_1% & add C513 0.1U_0402_16V4Z 19 Page44 : Add C554 for MIC_R Add R440, R695 (0_0603_5%) & J4, J5 for EMI request 20 Page45 : Add Echo Cancellation function 21 Page46 : Correct Headphone L & R signal Reserved C879 for EMI request Modify MIC Jack circuit add R741, R775, R776, L54, C876 Change JP44 from 14 pin to 16 pin 22 Page48 : H27 connect to GNDA B B 23 Page49 : Add R290, R238, R497, Q10, Q7, Q29 Change R317 to 200K_0402_5% Change R586 to 510K_0402_5% A A 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HW PIR Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 58 of 59 D m o c e u l b p o t p a l w W w D C C B B A A 2005/06/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR PIR Size B Date: Document Number Rev 0.3 HBL50 LA-2921P Sheet Friday, November 11, 2005 59 of 59 m o c e u l b p o t p a l w W w ... 4.7U_0805_10V4Z LAN_MIDI3+ LAN_MIDI3LAN_MIDI2+ LAN_MIDI2LAN_MIDI1+ LAN_MIDI1LAN_MIDI0+ LAN_MIDI0+3VALW SPROM_CS SPROM_CLK SPROM_DOUT SPROM_DIN DC_D8/(PCIE_TST) R187 1K_0402_5% 8789@ U8 LAN_MIDI3+ LAN_MIDI3LAN_MIDI2+... LAN_MIDI2LAN_MIDI1+ LAN_MIDI1LAN_MIDI0+ LAN_MIDI0- +3VALW 1K_0402_5% 0.1U_0402_16V4Z RESERVED_N8/(REFCLK+) RESERVED_P8/(REFCLK-) 5787(10/100/1000 LAN) Stuff +2.5V_LAN 0.1U_0402_16V4Z N8 P8 +LAN_18_12... +2.5V_LAN +3VALW 1 MCT1 MX1+ MX1- 24 23 22 RJ45_MIDI3RJ45_MIDI3+ 34 LAN_MIDI234 LAN_MIDI2+ LAN_MIDI2LAN_MIDI2+ TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_MIDI2RJ45_MIDI2+ 34 LAN_MIDI134 LAN_MIDI1+