5 SYSTEM DC/DC Project code: 91.4CG01.001 PCB P/N : 48.4CG01.0SA REVISION : 08245-SA JV50 Block Diagram 42 ISL62392 INPUTS OUTPUTS 5V_S5(6A) 3D3V_S5(7A) DCBATOUT 5V_AUX_S5 3D3V_AUX_S5 SMSC Mobile CPU CLK GEN D SYSTEM DC/DC EMC2102 Penryn ICS9LPRS365B PCB STACKUP 34 TOP L1 TPS51124 GND L2 INPUTS S L3 4, HOST BUS DDR3 667/800/1066MHz@1.05V VRAM 64MbX16X4 512M Cantiga 800/1066 16,17 MHz PCIex16 AGTL+ CPU I/F VGA BOTTOM L6 1D05V_S0(9A) 1D5V_S3(12A) RT9026 44 DDR_VREF_S3 (1.2A) 1D5V_S3 RT9018 44 1D5V_S3 1D1V_S0(2A) 18 TPS51117 CRT 6,7,8,9,10,11 19 C-Link0 RTS5159 45 DCBATOUT FBVDD(4A) CHARGER MS/MS Pro/xD /MMC/SD CardBus USB ISL88731A 31 47 INPUTS OUTPUTS DCBATOUT BT+ C C ICH9M PCIe ports LINE IN LAN PCI/PCI BRIDGE TXFM Giga LAN ACPI 2.0 29 BCM5764 SATA CPU DC/DC RJ45 26 25 ISL6266A 26 12 USB 2.0/1.1 ports Codec 18 High Definition Audio AZALIA LPC I/F New Card Serial Peripheral I/F ALC888S 32 Matrix Storage Technology(DO) 27 Active Managemnet Technology(DO) MIC In 12,13,14,15 INT.SPKR PWR SW TPS2231 32 VCC_CORE 38A LPC BUS LINE OUT USB SATA MODEM MDC Card 30 OUTPUTS DCBATOUT VGA_CORE 13A ISL6263A 30 29 47 INPUTS GFXCORE MAX9789A RJ11 DCBATOUT VGA_CORE Mini Card 33 3G card OP AMP 29 OUTPUTS RT8202A Mini Card Wire LAN 33 PCIe 29 1.5W 41 INPUTS ETHERNET (10/100/1000MbE) Int MIC B D DCBATOUT LCD LVDS, CRT I/F X4 DMI 400MHz L5 20 52~57 INTEGRATED GRAHPICS 800/1066 16,17 MHz L4 HDMI N10M-GE-1 DDR Memory I/F DDR3 S GND 43 OUTPUTS Mini USB Blue Tooth HDD SATA 21 23 SPI BIOS KBC (2MB) 36 Winbond Camera WPCE773 35 SATA Finger Printer ODD SATA 22 37 USB Port 24 Touch Pad 37 46 INPUTS OUTPUTS DCBATOUT VCC_GFXCORE (7A) LPC B DEBUG CONN.36 MEDIA KEY 38 INT KB 35 A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title BLOCK DIAGRAM Size A2 Date: Document Number Rev SB JV50 Sheet Thursday, January 08, 2009 1 of 60 A B ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5 Signal Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK C page 92 Comment ICH9 EDS 642879 Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) This signal has weak internal pull-down CL_CLK[1:0] PULL-UP 20K CL_DATA[1:0] PULL-UP 20K CL_RST0# PULL-UP 20K DPRSLPVR/GPIO16 PULL-DOWN 20K ENERGY_DETECT PULL-UP 20K HDA_BIT_CLK PULL-DOWN 20K HDA_DOCK_EN#/GPIO33 PULL-UP 20K HDA_RST# PULL-DOWN 20K HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K HDA_SYNC PCIE config1 bit0, Rising Edge of PWROK This signal has a weak internal pull-down Sets bit0 of RPC.PC(Config Registers:Offset 224h) GNT2#/ GPIO53 PCIE config2 bit2, Rising Edge of PWROK This signal has a weak internal pull-up Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high GPIO20 Reserved GNT1#/ GPIO51 ESI Strap (Server Only) Rising Edge of PWROK ESI compatible mode is for server platforms only This signal should not be pulled low for desttop and mobile GNT3#/ GPIO55 Top-Block Swap Override Rising Edge of PWROK Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space) Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down Boot BIOS Destination Selection 0:1 Rising Edge of PWROK Integrated TPM Enable, Rising Edge of CLPWROK Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10) GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC Sample low: the Integrated TPM will be disabled Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI GPIO49 SATALED# SPKR TP3 GPIO33/ HDA_DOCK _EN# ICH9M Integrated Pull-up and Pull-down Resistors DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK applications and required to be high for mobile applications SIGNAL Montevina Platform Design guide 22339 page 218 Rev.1.5 Pin Name Resistor Type/Value HDA_SYNC GLAN_DOCK# E CantigaDchipset and ICH9M I/O controller Hub strapping configuration CFG[2:0] CFG[4:3] CFG8 CFG[15:14] CFG[18:17] Strap Description 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved FSB Frequency Select PULL-UP 20K GPIO[20] PULL-DOWN 20K GPIO[49] PULL-UP 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K PCI Express Lane Reversal Rising Edge of PWROK No Reboot Rising Edge of PWROK Signal has weak internal pull-up Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) PWRBTN# PULL-UP 20K SATALED# PULL-UP 15K If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature) The status is readable via the NO REBOOT bit SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K SPI_MOSI PULL-DOWN 20K SPI_MISO PULL-UP 20K XOR Chain Entrance Rising Edge of PWROK This signal should not be pull low unless using XOR Chain testing SPKR PULL-DOWN 20K TACH_[3:0] PULL-UP 20K Flash Descriptor Security Override Strap Rising Edge of PWROK Sampled low:the Flash Descriptor Security will be overridden If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister TP[3] PULL-UP 20K USB[11:0][P,N] PULL-DOWN 15K Reserved CFG5 DMI x2 Select CFG6 iTPM Host Interface = DMI x2 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) = Transport Layer Security (TLS) cipher suite with no confidentiality = TLS cipher suite with confidentiality (default) CFG7 Intel Management engine Crypto strap CFG9 PCIE Graphics Lane = Reverse Lanes,15->0,14->1 ect 1= Normal operation(Default):Lane Numbered in order CFG10 PCIE Loopback enable = Enable (Note 3) 1= Disabled (default) PULL-DOWN 20K The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller GNT[3:0]#/GPIO[55,53,51] 0.5 Configuration CFG[13:12] CFG16 CFG19 00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3) 11 = Disabled (default) XOR/ALL FSB Dynamic ODT = Dynamic ODT Disabled = Dynamic ODT Enabled (Default) DMI Lane Reversal = Normal operation(Default): Lane Numbered in Order = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) CFG20 Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe = Only Digital Display Port or PCIE is operational (Default) =Digital display Port and PCIe are operting simulataneously via the PEG port =No SDVO Card Present (Default) SDVO_CTRLDATA SDVO Present = SDVO Card Present = LFP Disabled (Default) L_DDC_DATA Local Flat Panel (LFP) Present 1= LFP Card Present; PCIE disabled NOTE: All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware This 'Soft-Strap' is activated only after enabling iTPM via CFG6 Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time 2 JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Reference Size A3 Date: A B C D Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet E of 60 A C D E 3D3V_S0 1D05V_S0 SB 1202 SB 1202 SB 1202 SB 1202 C418 DY 2 1 2 2 1 2 1 2 2 1 2 C454 SCD1U16V2ZY-2GP C448 SCD1U16V2ZY-2GP SB 1202 3D3V_S0 C445 SCD1U16V2ZY-2GP C419 DY SCD1U16V2ZY-2GP C430 DY SCD1U16V2ZY-2GP C416 SC4D7U6D3V3KX-GP C436 SCD1U16V2ZY-2GP C444 SCD1U16V2ZY-2GP C435 SCD1U16V2ZY-2GP C417 DY SCD1U16V2ZY-2GP C450 DY SC4D7U6D3V3KX-GP C455 DY SCD1U16V2ZY-2GP C457 SC1U16V3ZY-GP SC4D7U6D3V3KX-GP C456 3D3V_VDD48_S0 SCD1U16V2ZY-2GP R554 0R0603-PAD 3D3V_S0 B SB 1202 1D05V_S0 3D3V_VDD48_S0 X5 X-14D31818M-35GP 1 82.30005.891 C452 SC33P50V2JN-3GP UMA 4,7 31 PCLKCLK2 CPU_SEL2_R PCLKCLK5 3D3V_S0 SRN10KJ-6-GP RN46 13 13 CLK_ICH14 CLK48_ICH 35 PCLK_KBC 13 PCLK_ICH C451 CPU_SEL2_R CLK48 PCLKCLK4 PCLKCLK5 DY 36,51 PCLK_FWH 63 13 CLK_PWRGD 10KR2J-3-GP 2R249 DY 10 11 12 13 14 -1 PCLK_ICH PCLK_KBC SRCT10 SRCC10 SCLK SDATA SRCT11/CR#_H SRCC11/CR#_G CK_PWRGD/PD# SRCT9 SRCC9 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC SC33P50V2JN-3GP 4,7 CPU_SEL1 CPU_SEL2_R 64 SC33P50V2JN-3GP 55 SC33P50V2JN-3GP FSLB/TEST_MODE REF0/FSLC/TEST_SEL 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 NC#55 SC33P50V2JN-3GP SC33P50V2JN-3GP 18 15 CLK48_ICH EC25 EC24 EC23 EC39 EC48 SRCT6 SRCC6 GND48 GNDPCI GNDREF PCLK_FWH PCI_STOP# CPU_STOP# PCLKCLK0 PCLKCLK1 R255 33R2J-2-GP PCLKCLK2 1PCLKCLK3 TPAD14-GP TP158 PCLKCLK4 -1 PCLKCLK5 SC47P50V2JN-3GP SRN33J-7-GP CLK_ICH14 SRCT7/CR#_F SRCC7/CR#_E modify by RF 15,16,17 SMBC_ICH 15,16,17 SMBD_ICH 61 60 CLK_CPU_BCLK CLK_CPU_BCLK# CPU 58 57 CLK_MCH_BCLK CLK_MCH_BCLK# NB 54 53 CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13 SB DMI 51 50 CLK_PCIE_NEW 32 CLK_PCIE_NEW# 32 NEWCARD 48 47 CLK_PCIE_PEG 52 CLK_PCIE_PEG# 52 GPU 41 42 CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25 LAN 37 38 CLK_PCIE_MINI1 33 CLK_PCIE_MINI1# 33 WLAN 34 35 CLK_MCH_3GPLL CLK_MCH_3GPLL# NB CLK 31 32 CLK_PCIE_MINI2 33 CLK_PCIE_MINI2# 33 3G USB_48MHZ/FSLA GND CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 65 CPU_SEL2 45 44 13 PM_STPPCI# 13 PM_STPCPU# RN48 17 CPUT1_F CPUC1_F GND GNDSRC GNDSRC GNDSRC GNDCPU GND 4,7 2K2R2J-2-GP CLK48 33R2J-2-GP R2512 R253 CPUT0 CPUC0 X1 X2 22 30 36 49 59 26 CPU_SEL0 CLK48_5158E GEN_XTAL_IN VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO GEN_XTAL_OUT PCLKCLK4 R254 10KR2J-3-GP 3D3V_S0 U24 VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 C453 SC33P50V2JN-3GP DIS 16 46 62 23 CL=20pF±0.2pF SB 1202 R260 10KR2J-3-GP 19 27 43 52 33 56 3D3V_S0 SRCT0/DOTT_96 SRCC0/DOTC_96 40 39 28 29 CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 SB SATA RN42 SRN33J-5-GP-U VGA_XIN1 52 OSC_SPREAD GPU DREFCLK_1 DREFCLK_1# RN44 SRN0J-6-GP DREFCLK DREFCLK# 3D3V_S0 RN76 SRN0J-6-GP DREFSSCLK DREFSSCLK# 24 25 DREFSSCLK_1 DREFSSCLK_1# 20 21 DIS -1 UMA ICS9LPRS365BKLFT-GP-U 71.09365.A03 UMA EMI capacitor for Antenna team suggestion -1 RN47 SRN10KJ-6-GP RN45 13 25 33 Byte 5, bit = PCI0 enabled (default) 1= CR#_A enabled Byte 5, bit controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PCI0/CR#_A PCI1/CR#_B Byte 5, bit = PCI1 enabled (default) 1= CR#_B enabled Byte 5, bit controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair PCI2/TME = Overclocking of CPU and SRC Allowed = Overclocking of CPU and SRC NOT allowed PCI3 PCI4/27M_SEL = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# PCI_F5/ITP_EN =SRC8/SRC8# = ITP/ITP# SRCT3/CR#_C Byte 5, bit = SRC3 enabled (default) 1= CR#_C enabled Byte 5, bit controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair SATACLKREQ# CLK_MCH_OE# LAN_CLKREQ# WLAN_CLKREQ# PCLKCLK0 PCLKCLK1 CR#_H CR#_G B NB VGA_XIN1 EC68 DY OSC_SPREAD EC69 DY NB 2 SC33P50V2JN-3GP SC33P50V2JN-3GP SEL2 SEL1 SEL0 FSC FSB FSA DY CPU FSB 100M 133M 166M 200M 266M X 533M 667M 800M 1067M SRN470J-3-GP PIN NAME DESCRIPTION SRCC3/CR#_D Byte 5, bit = SRC3 enabled (default) 1= CR#_D enabled Byte 5, bit controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair SRCC7/CR#_E Byte 6, bit = SRC7# enabled (default) 1= CR#_F controls SRC6 SRCT7/CR#_F Byte 6, bit = SRC7 enabled (default) 1= CR#_F controls SRC8 SRCC11/CR#_G Byte 6, bit = SRC11# enabled (default) 1= CR#_G controls SRC9 SRCT11/CR#_H Byte 6, bit = SRC11 enabled (default) 1= CR#_H controls SRC10 0 0 C 0 1 1 0 JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Clock Generator Size Document Number Rev JV50 Date: A 52 DY ICS9LPRS365YGLFT setting table PIN NAME DESCRIPTION CR#_H CR#_G D Thursday, January 08, 2009 SB Sheet E of 60 A C D E H_A#[35 3] H_A#[35 3] H_DINV#[3 0] M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 TPAD14-GP TP97 RSVD_CPU_11 B1 H_HIT# H_HITM# 6 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#1 TP28 TP27 TP26 TP32 TP29 TP30 TP34 TP50 TP31 TP49 TP33 TP88 CPU1B PROCHOT# THRMDA THRMDC STPCLK# LINT0 LINT1 SMI# THERMTRIP# HCLK BCLK0 BCLK1 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_THERMDA TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP H_THERMDC C116 SC2200P50V2KX-2GP DY 1D05V_S0 Close to NB R89 68R2-GP CPU_PROCHOT#_1 D21 A24 B25 H_DSTBN#0 H_DSTBP#0 H_DINV#0 R97 2DY 0R2J-2-GP C90 CPU_PROCHOT#_R PM_THRMTRIP-A# 7,12,39 A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# 41 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 SC47P50V2JN-3GP modify by RF DY H_THERMDA 34 H_THERMDC 34 C7 PM_THRMTRIP# ICH9 and MCH PH @ page48 should connect to without T-ing 1D05V_S0 Layout Note: "CPU_GTLREF0" 0.5" max length 6 1KR2F-3-GP R312 R309 2KR2F-3-GP KEY_NC BGA479-SKT6-GPU7 62.10079.001 2nd = 62.10053.401 H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_GTLREF0 DY C526TPAD14-GP TP87 TPAD14-GP TP25 TPAD14-GP TP180 3,7 3,7 3,7 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 OF N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 TEST1 C23 TEST2 D25 1RSVD_CPU_12 C24 TEST4 AF26 1RSVD_CPU_13 AF1 1RSVD_CPU_14 A26 B22 B23 C21 CPU_SEL0 CPU_SEL1 CPU_SEL2 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 MISC BSEL0 BSEL1 BSEL2 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R71 R67 R57 R60 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP 2 2 H_PWRGD 12,39,51 H_CPUSLP# H_PSI# 41 1D05V_S0 R54 54D9R2F-L1-GP XDP_TDI R55 54D9R2F-L1-GP XDP_BPM#5 R46 XDP_TDO R47 R113 TEST1 1KR2J-1-GP DY TEST2 R114 1KR2J-1-GP C525 2DY TEST4 SCD1U10V2KX-4GP Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals 54D9R2F-L1-GP 54D9R2F-L1-GP DY 51R2F-2-GP DY 3D3V_S0 XDP_DBRESET# DY R119 Layout Note: Comp0, connect with Zo=27.4 ohm, make trace length shorter than 0.5" Comp1, connect with Zo=55 ohm, make trace length shorter than 0.5" SC100P50V2JN-3GP C102 DY XDP_TMS H_DPRSTP# 7,12,41 H_DPSLP# 12 H_DPWR# BGA479-SKT6-GPU7 H_CPURST# modify by RF DATA GRP2 H_D#[63 0] DY DATA GRP3 H_TRDY# G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 H_LOCK# H_CPURST# 6,51 H_RS#[2 0] H_RS#0 H_RS#1 H_RS#2 H_DSTBP#[3 0] SC47P50V2JN-3GP C1 F3 F4 G3 G2 C104 12 THERMAL A20M# FERR# IGNNE# RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 H_INIT# H4 D5 C6 B4 A3 H_BREQ#0 H_IERR# D20 B3 H_DSTBN#[3 0] R88 56R2J-4-GP 1 H_STPCLK# H_INTR H_NMI H_SMI# BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# F1 H_D#[63 0] Place testpoint on H_IERR# with a GND 0.1" away 12 12 12 12 H_DSTBP#[3 0] SC1KP50V2KX-1GP A6 A5 C4 H_DEFER# H_DRDY# H_DBSY# H_DINV#[3 0] H_DSTBN#[3 0] 1D05V_S0 H_A20M# H_FERR# H_IGNNE# HIT# HITM# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# H5 F21 E1 6 DATA GRP1 H_ADSTB#1 12 12 12 BR0# IERR# INIT# LOCK# ICH Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 DEFER# DRDY# DBSY# RESET# RS0# RS1# RS2# TRDY# REQ0# REQ1# REQ2# REQ3# REQ4# ADDR GROUP H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_BNR# H_BPRI# K3 H2 K2 J3 L1 H1 E2 G5 DATA GRP0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 H_REQ#[4 0] A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# TPAD14-GP RESERVED 6 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 TP74 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 OF CONTROL CPU1A B R105 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# H_INIT# H_CPURST# 1KR2J-1-GP DY XDP_TCK R32 54D9R2F-L1-GP XDP_TRST# R33 54D9R2F-L1-GP 1 1 1 TP76 TP95 TP114 TP81 TP78 TP92 TP86 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP Place these TP on button-side, easy to measure JV50 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (1 of 2) Size All place within 2" to CPU Wistron Corporation Document Number Rev JV50 Date: A B C D Thursday, January 08, 2009 SB Sheet E of 60 B C 1 2 1 2 1 2 1 2 1 C537 SC10U6D3V5MX-3GP 1 C536 SC10U6D3V5MX-3GP C547 SC10U6D3V5MX-3GP C548 SC10U6D3V5MX-3GP 1 C539 SC10U6D3V5MX-3GP C552 SC10U6D3V5MX-3GP C538 SC10U6D3V5MX-3GP DY C553 SC10U6D3V5MX-3GP C52 SC10U6D3V5MX-3GP 1 2 C57 DY C83 C80 C79 1 2 C58 C75 C84 SC4D7U6D3V3KX-GP GAP-CLOSE-PWR C67 SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP 1D05V_S0 G2 SCD1U10V2KX-4GP 1D05V_S0_CPU SB 1208 1D05V_S0 SCD1U10V2KX-4GP DY layout note: "1D5V_VCCA_S0" as short as possible 1D5V_S0 AE7 100R2F-L1-GP-U AF7 2 R25 C603 FCM1608KF-1-GP L18 C6062nd = 68.00248.061 SC10U6D3V5MX-3GP 41 SCD01U16V2KX-3GP H_VID[6 0] VCC_CORE H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 1D5V_VCCA_S0 B26 C26 VCC_SENSE 41 VSS_SENSE 41 VSSSENSE DY SCD1U10V2KX-4GP VCCSENSE C51 TPAD14-GP TP23 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 AD6 AF5 AE5 AF4 AE3 AF3 AE2 C50 SC10U6D3V5MX-3GP VID0 VID1 VID2 VID3 VID4 VID5 VID6 C53 SC10U6D3V5MX-3GP VCCA VCCA C88 SC10U6D3V5MX-3GP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 C89 SC10U6D3V5MX-3GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SCD1U10V2KX-4GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SCD1U10V2KX-4GP OF C87 SC10U6D3V5MX-3GP A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 DY E SB 1209 SC10U6D3V5MX-3GP CPU1C DY C55 SCD1U10V2KX-4GP DY C85 SCD1U10V2KX-4GP VCC_CORE C56 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C86 DY VCC_CORE D VCC_CORE VCC_CORE A Layout Note: R24 VCCSENSE and VSSSENSE lines should be of equal length 100R2F-L1-GP-U BGA479-SKT6-GPU7 Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line CPU1D A4 A8 A11 A14 A16 A19 A23 TP_AF2_CPU AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 OF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 TP_AE26_CPU TP_A2_CPU A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 TP_A25_CPU AF25 TP174 TPAD14-GP TP98 TPAD14-GP TP181 TPAD14-GP BGA479-SKT6-GPU7 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (2 of 2) Size Document Number Rev JV50 Date: A B C D Thursday, January 08, 2009 SB Sheet E of 60 1 OF 10 NB1A H_A#[35 3] H_D#[63 0] H_D#[63 0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING routing Trace width and Spacing use 10 / 20 mil 1D05V_S0 D R381 221R2F-2-GP H_SWING Resistors and Capacitors close MCH 500 mil ( MAX ) R382 100R2F-L1-GP-U 2 C619 SCD1U10V2KX-4GP H_SWING C H_RCOMP routing Trace width and Spacing use 10 / 20 mil R380 H_RCOMP 24D9R2F-L-GP Place them near to the chip ( < 0.5") B F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST R370 1KR2F-3-GP 4,51 H_CPURST# H_CPUSLP# H_AVREF C614 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_A#[35 3] D H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ#0 H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 H_DSTBN#[3 0] H_DSTBP#[3 0] C H_DINV#[3 0] H_DSTBN#[3 0] H_DSTBP#[3 0] H_REQ#[4 0] H_RS#[2 0] B 4 CANTIGA-GM-GP-U-NF 71.CNTIG.00U 2 C12 E11 A11 B11 SCD1U16V2ZY-2GP R389 2KR2F-3-GP C5 E3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_DINV#[3 0] H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 1D05V_S0 H_SWING H_RCOMP H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 JV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size Date: Document Number Cantiga (1 of 6) JV50 Thursday, January 08, 2009 Rev SB Sheet of 60 1D05V_S0 OF 10 NB1B OF 10 RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# CLK DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# AR24 AR21 AU24 AV20 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 16 16 17 17 18 35 18 CLK_DDC_EDID 18 DAT_DDC_EDID 18 GMCH_LCDVDD_ON BC28 AY28 AY36 BB36 M_CKE0 M_CKE1 M_CKE2 M_CKE3 16 16 17 17 BA17 AY16 AV16 AR13 M_CS0# M_CS1# M_CS2# M_CS3# 16 16 17 17 BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 16 16 17 17 TPAD14-GP TP189 R183 0R0402-PAD M_RCOMPP M_RCOMPN BF28 BH28 SM_RCOMP_VOH SM_RCOMP_VOL AV42 AR36 BF17 BC36 DDR2 : connect to GND SM_REXT R4441 499R2F-2-GP DDR3_DRAMRST# DDR3_DRAMRST# SM_PWROK 39 DDR_VREF_S3_1 0.75V 16,17 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# F43 E43 L32 G32 M32 LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID M33 K33 J33 GMCH_LCDVDD_ON LIBG L_LVBG LVDS_VREF M29 C44 B43 E37 E38 C41 C40 B37 A37 18 GMCH_TXACLK18 GMCH_TXACLK+ 18 GMCH_TXBCLK18 GMCH_TXBCLK+ BG22 BH21 B38 A38 E41 F41 LCTLA_CLK L_BKLTCTL GMCH_BL_ON CLK_MCH_3GPLL CLK_MCH_3GPLL# C335 3 18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2- H47 E46 G40 A40 18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+ H48 D45 F40 B40 18 GMCH_TXBOUT018 GMCH_TXBOUT118 GMCH_TXBOUT2- A41 H38 G37 J37 18 GMCH_TXBOUT0+ 18 GMCH_TXBOUT1+ 18 GMCH_TXBOUT2+ B42 G38 F37 K37 TV_DACA TV_DACB TV_DACC F25 H25 K25 13,34 13,25,31,32,33,35,36,51,52 PWROK PLT_RST1# 100R2J-2-GP R203 C324 SC100P50V2JN-3GP DY SB 1202 4,12,39 PM_THRMTRIP-A# R192 0R0402-PAD B R195 PM_DPRSLPVR_MCH 0R0402-PAD BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47 13 13 13 13 GMCH_BLUE 19 GFX_VR_EN E28 GMCH_GREEN G28 J28 G29 GMCH_DDCCLK GMCH_DDCDATA R189 GMCH_HS 0R0402-PAD R188 2GMCH_VS 0R0402-PAD 46 GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 TV_RTN TV_DCONSEL_0 TV_DCONSEL_1 H32 J32 J29 E29 L29 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF CRT_BLUE DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC CRT_IREF 1K02R2F-1-GP TSATN# B12 MCH_TSATN# B28 B30 B29 C29 A28 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC R201 1KR2F-3-GP CL_CLK0 13 CL_DATA0 13 PWROK 13,34 CL_RST#0 13 C288 GMCH_HDMI_CLK 20 GMCH_HDMI_DATA 20 CLK_MCH_OE# MCH_ICH_SYNC# 13 R200 499R2F-2-GP FOR Cantiga:500 ohm Teenah: 392 ohm ACZ_SDIN3 UMA C220 C648 C654 C228 C233 C658 C237 C239 C265 C264 C269 C660 C671 C666 C680 C679 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PEG_TXP0_L PEG_TXP1_L PEG_TXP2_L PEG_TXP3_L PEG_TXP4_L PEG_TXP5_L PEG_TXP6_L PEG_TXP7_L PEG_TXP8_L PEG_TXP9_L PEG_TXP10_L PEG_TXP11_L PEG_TXP12_L PEG_TXP13_L PEG_TXP14_L PEG_TXP15_L DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 C213 C647 C651 C222 C229 C663 C234 C245 C259 C253 C266 C657 C667 C664 C672 C686 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 UMA UMA C600 C605 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN0_L_1 PEG_TXP0_L_1 UMA UMA UMA C596 C598 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN1_L_1 PEG_TXP1_L_1 UMA PEG_TXN2_L PEG_TXP2_L UMA UMA C589 C592 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN2_L_1 PEG_TXP2_L_1 UMA PEG_TXN3_L PEG_TXP3_L UMA UMA C568 C561 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN3_L_1 PEG_TXP3_L_1 UMA R555 PEG_RXP3 ACZ_BIT_CLK ACZ_SYNC_R ACZ_RST#_R ACZ_SDATAOUT_R ACZ_SDIN3 2UMA HDMI_DETECT#_L GMCH_RED GMCH_GREEN GMCH_BLUE 12 2 52 C HDMI_DATA2- 20,55 HDMI_DATA2+ 20,55 RN83 SRN0J-10-GP-U HDMI_DATA1- 20,55 HDMI_DATA1+ 20,55 RN84 SRN0J-10-GP-U HDMI_DATA0- 20,55 HDMI_DATA0+ 20,55 RN85 SRN0J-10-GP-U HDMI_CLK- 20,55 HDMI_CLK+ 20,55 B 2UMA HDMI_DETECT# 20 0R2J-2-GP SCD01U16V2KX-3GP 2 C756 C759 SC2D2U6D3V3MX-1-GP EC21DY HDA_BCLK SC12P50V2JN-3GP RN32 GMCH_BL_ON GMCH_LCDVDD_ON SCD01U16V2KX-3GP 2 C757 C760 UMA TV_DACC TV_DACB TV_DACA R162 0R2J-2-GP RN33 GMCH_VS GMCH_HS A DIS SRN0J-10-GP-U FOR Discrete,change to ohm (66.R0036.A8L) 2K37R2F-GP DIS CRT_IREF UMA/DIS R178 100KR2F-L1-GP R384 RN31 SRN75J-1-GP SC2D2U6D3V3MX-1-GP UMA SRN100KJ-6-GP LIBG 2 R446 1KR2F-3-GP 46 UMA/DIS layout take note UMA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SRN10KJ-5-GP RN35 Title Cantiga (2 of 6) Size Document Number SRN10KJ-5-GP Rev SB JV50 Date: PEG_TXP[15 0] RN82 SRN0J-10-GP-U FOR Discrete change RN to ohm (66.R0036.A8L) 1 2 DY R61 1KR2F-3-GP SM_RCOMP_VOH GFXVR_EN 52 SRN150F-1-GP R441 3K01R2F-3-GP GFXVR_EN PEG_TXN[15 0] 12 ACZ_BIT_CLK 12 ACZ_SYNC_R 12 ACZ_RST#_R 12 ACZ_SDATAOUT_R SM_RCOMP_VOL 2 2 2 2 2 2 2 2 PEG_TXN1_L PEG_TXP1_L 1D5V_S3 MCH_TSATN# PM_EXTTS#0 PM_EXTTS#1 1 1 1 1 1 1 1 1 RN30 R445 RN34 DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS PEG_TXN0_L PEG_TXP0_L UMA R387 56R2J-4-GP PEG_TXN0_L PEG_TXN1_L PEG_TXN2_L PEG_TXN3_L PEG_TXN4_L PEG_TXN5_L PEG_TXN6_L PEG_TXN7_L PEG_TXN8_L PEG_TXN9_L PEG_TXN10_L PEG_TXN11_L PEG_TXN12_L PEG_TXN13_L PEG_TXN14_L PEG_TXN15_L 52 33R2J-2-GP 1D05V_S0 LCTLA_CLK LCTLB_DATA J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PEG_RXP[15 0] SB 1202 SRN33J-4-GP 3D3V_S0 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 71.CNTIG.00U CRT_IREF routing Trace width use 20 mil RN36 71.CNTIG.00U A H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 D R419 HDA_BCLK HDA_SYNC HDA_RST# HDA_SDO CANTIGA-GM-GP-U-NF 52 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 0R2J-2-GP HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC modify by RF PEG_RXN[15 0] H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 CANTIGA-GM-GP-U-NF MCH_CLVREF N28 M28 G36 E36 K36 CLK_MCH_OE# H36 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 CRT_GREEN FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm 1D05V_S0 AH37 AH36 AN36 AJ35 AH34 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 UMA R161 GFXVR_EN C34 GMCH_BLUE GMCH_RED GMCH_RED 19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC for HDMI port C NC 13,41 PM_DPRSLPVR PM SB 1202 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 19 19 GMCH_GREEN GFX_VID[4 0] B33 B32 G33 F33 E33 TVA_DAC TVB_DAC TVC_DAC CFG16 13 13 13 13 19 GMCH_VSYNC GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 2K21R2F-GP AD35 AE44 AF46 AH43 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DY PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR R556 R29 B7 PM_EXTTS#0 N33 PM_EXTTS#1 P32 AT40 RSTIN# AT11 NB_THERMTRIP# T20 PM_DPRSLPVR_MCH R32 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 Close to GMCH as 500 mils DY CFG20 13 PM_SYNC# 4,12,41 H_DPRSTP# 16,17 PM_EXTTS#0 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 M_RCOMPN R442 80D6R2F-L-GP LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13 AE35 AE43 AE46 AH42 49D9R2F-GP SC47P50V2JN-3GP 2 CFG9 ME CFG20 2K21R2F-GP MISC 4K02R2F-GP DY DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 HDA DY R385 1 R193 CFG16 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AE40 AE38 AE48 AH40 C31 E32 SCD1U10V2KX-4GP M_RCOMPP CFG CFG9 R443 80D6R2F-L-GP 3D3V_S0 DMI 1D5V_S3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DMI_TXN0 13 DMI_TXN1 13 DMI_TXN2 13 DMI_TXN3 13 L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 VGA T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CPU_SEL0 CPU_SEL1 CPU_SEL2 GRAPHICS VID 3,4 3,4 3,4 C AE41 AE37 AE47 AH39 L_CTRL_DATA L_DDC_CLK L_DDC_DATA PEG_CMP T37 T36 PEG_COMPI PEG_COMPO TV H24 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 R196 C270 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK GRAPHICS RESERVED#AY21 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 16 16 17 17 LVDS AY21 BG23 BF23 BH18 BF18 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 PCI-EXPRESS RESERVED#B31 RESERVED#B2 RESERVED#M1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 AP24 AT21 AV24 AU20 B31 B2 M1 RSVD D SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24 SCD1U10V2KX-4GP DDR CLK/ CONTROL/COMPENSATION NB1C M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 Thursday, January 08, 2009 Sheet of 60 B M_A_BS#0 16 M_A_BS#1 16 M_A_BS#2 16 BB20 BD20 AY20 M_A_RAS# 16 M_A_CAS# 16 M_A_WE# 16 MEMORY A M_A_DM[7 0] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_DQS[7 0] M_A_DQS#[7 0] M_A_A[14 0] M_A_DM[7 0] M_A_DQS[7 0] 16 16 M_A_DQS#[7 0] M_A_A[14 0] 16 16 M_B_DQ[63 0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 OF 10 NB1E AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# BC16 BB17 BB33 M_B_BS#0 17 M_B_BS#1 17 M_B_BS#2 17 AU17 BG16 BF14 M_B_RAS# 17 M_B_CAS# 17 M_B_WE# 17 D M_B_DM[7 0] B SA_RAS# SA_CAS# SA_WE# 17 M_B_DQ[63 0] BD21 BG18 AT25 MEMORY SA_BS_0 SA_BS_1 SA_BS_2 SYSTEM C SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 OF 10 NB1D AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SYSTEM D M_A_DQ[63 0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 DDR 16 M_A_DQ[63 0] DDR CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF 71.CNTIG.00U 71.CNTIG.00U SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 M_B_DM[7 0] M_B_DQS[7 0] M_B_DQS[7 0] M_B_DQS#[7 0] 17 17 M_B_DQS#[7 0] M_B_A[14 0] M_B_A[14 0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 17 C 17 B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (3 of 6) Size Document Number Rev JV50 Date: Thursday, January 08, 2009 SB Sheet of 60 1D5V_S3 UMA C278 UMA C279 UMA C612 C289 UMA C271 C286 DY 2 UMA C275 SCD47U6D3V2KX-GP DY C285 1 DY 2 1 2 2 UMA C302 DY SCD1U10V2KX-4GP DY C282 Coupling CAP AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32 Place on the Edge Coupling CAP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC D VCC CORE AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 POWER 1 1 1 2 2 2 C284 SCD1U10V2KX-4GP POWER C280 SCD1U10V2KX-4GP SB 1202 C276 SCD1U10V2KX-4GP UMA C273 SCD1U10V2KX-4GP UMA C277 SC1U10V3ZY-6GP DY C292 SC10U6D3V5MX-3GP VCC SM C281 SCD22U10V2KX-1GP -1 TC18 SC4D7U6D3V3KX-GP VCC GFX NCTF C249 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP DY C274 VCC_GFXCORE -1 SC4D7U6D3V3KX-GP VCC 1 2 2 2 ST330U2D5VBM-GP Place on the Edge SB 1202 C SC1U10V3KX-3GP C320 C340 SC1U10V3KX-3GP C298 SCD22U10V2KX-1GP SCD22U10V2KX-1GP C329 C347 71.CNTIG.00U C290 SCD1U10V2KX-4GP AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF CANTIGA-GM-GP-U-NF 2 VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH C350 SCD1U10V2KX-4GP VCC SM LF VCC GFX C348 SC4D7U6D3V3KX-GP DY C308 SC4D7U6D3V3KX-GP DY 80.3371V.12L C323 SC4D7U6D3V3KX-GP C349 TC22 SC4D7U6D3V3KX-GP DY C359 1D5V_S3 C367 1D05V_S0 VCC NCTF FOR VCC SM C361 SCD1U10V2KX-4GP U60(ISL6263ACRZ-T-GP) place near Cantiga C287 Coupling CAP 370 mils from the Edge SCD1U10V2KX-4GP 71.CNTIG.00U DY SCD1U10V2KX-4GP VCC_AXG_SENSE VSS_AXG_SENSE CANTIGA-GM-GP-U-NF C291 SC4D7U6D3V3KX-GP AJ14 AH14 0R5J-1-GP SCD47U16V3ZY-3GP VCC_AXG_SENSE VSS_AXG_SENSE R439 SC4D7U6D3V3KX-GP C VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG OF 10 NB1F FOR VCC CORE 0R5J-1-GP DIS SC4D7U6D3V3KX-GP Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 1D05V_S0 DIS R438 SC4D7U6D3V3KX-GP VCC_GFXCORE W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 SC4D7U6D3V3KX-GP VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF SC4D7U6D3V3KX-GP VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM ST220U2D5VBM-2GP BA36 BB24 BD16 BB21 AW16 AW13 AT13 46 VCC_AXG_SENSE 46 VSS_AXG_SENSE NB1G AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 D B VCC_GFXCORE OF 10 B place near Cantiga A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cantiga (4 of 6) Size Document Number Rev SB JV50 Date: Thursday, January 08, 2009 Sheet of 60 C263 SCD1U10V2KX-4GP C268 SCD47U6D3V2KX-GP C670 SC4D7U6D3V3KX-GP C662 SC2D2U6D3V3MX-1-GP C267 SC4D7U6D3V3KX-GP 2 2 1 A PEG A SM 1 1 2 1 2 1D05V_S0 DY C722 DY 1 C732 B DY SB 1202 2 DY 1 DY C675 UMA A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SC4D7U6D3V3KX-GP UMA R167 0R2J-2-GP C620 SCD47U6D3V2KX-GP VTTLF1 VTTLF2 VTTLF3 CANTIGA-GM-GP-U-NF C186 1 DY 456mA C650 SCD47U6D3V2KX-GP A8 L1 AB2 1D05V_S0 AH48 AF48 AH47 AG47 C739 C283 C676 SCD47U6D3V2KX-GP VTTLF VTTLF VTTLF VTTLF UMA 1782mA HV DMI VCC_DMI VCC_DMI VCC_DMI VCC_DMI 2 AXF SM CK A CK TV PEG V48 U48 V47 U47 U46 VCCD_LVDS VCCD_LVDS 71.CNTIG.00U SB 1202 C175 SC4D7U6D3V3KX-GP 1 UMA HDA DIS D TV/CRT 2 2 UMA 1 2 60.3mA 106mA C712 M38 L37 1D8V_SUS_DLVDS C235 VCCD_PEG_PLL C35 B35 A35 R396 0R0603-PAD R398 0R2J-2-GP SC10U6D3V5MX-3GP C690 50mA VCCD_HPLL VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG 3D3V_HV_S0 K47 1D8V_NB_S0 119mA SC10U6D3V5MX-3GP VCCD_QDAC AA47 VCC_HV VCC_HV VCC_HV 1D8V_TXLVDS_S0 DY SCD1U10V2KX-4GP C678 VCCD_TVDAC L28 LVDS 2 VCC_HDA M25 1D05V_RUN_PEGPLL SCD1U10V2KX-4GP UMA 1D5V_S3 SC10U6D3V5MX-3GP 157.2mA R153 0R0603-PAD C188 A32 AF1 1D8V_NB_S0 R159 SCD1U10V2KX-4GP SCD01U16V2KX-3GP 1 2 2 2 2 C SB 1202 SC1U10V3KX-3GP C634 VCCA_TV_DAC VCCA_TV_DAC BF21 BH20 BG20 BF20 C758 SCD1U10V2KX-4GP UMA SC4D7U6D3V3KX-GP VCC_TX_LVDS B24 A24 1D5VRUN_QDAC VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK C751 SC10U6D3V5MX-3GP C174 1D5VRUN_TVDAC SCD1U10V2KX-4GP 74.G1117.B3C UMA C100 R448 0R0603-PAD SC1KP50V2KX-1GP C635 C715 0R2J-2-GP G1117-18T63UF-GP 200mA B22 B21 A21 SC4D7U6D3V3KX-GP DY VCC_AXF VCC_AXF VCC_AXF SC4D7U6D3V3KX-GP VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF R383 0R2J-2-GP 1D5VRUN_QDAC PBY160808T-181Y-GP 58.7mA SCD1U10V2KX-4GP SCD01U16V2KX-3GP C243 DY 2 2 3D3V_S0 1D8V_NB_S0 C119 SC1U10V2ZY-GP DY VIN VOUT GND SC1U10V2ZY-GP DY C272 SC4D7U6D3V3KX-GP POWER C251 SCD1U10V2KX-4GP C750 SCD1U10V2KX-4GP 3D3V_S0_DAC_1 VCC_HDA R375 0R0603-PAD SCD1U10V2KX-4GP SCD1U10V2KX-4GP 1D5VRUN_TVDAC UMA I=1A U12 C616 1D5V_SUS_SM_CK AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 R386 0R2J-2-GP DY C691 SCD1U10V2KX-4GP C247 1D05V_S0 322mA SC4D7U6D3V3KX-GP SC1U10V3KX-3GP C305 SC1U10V3KX-3GP DY C293 1D5V_S0 UMA UMA VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM R377 0R0603-PAD 1D05V_SUS_MCH_PLL2 180ohm 100MHz SC4D7U6D3V3KX-GP DY C313 3D3V_S0_DAC 1D5V_S0 UMA C309 DY C205 SB 1202 DY SC2D2U6D3V3MX-1-GP 139.2mA C697 SCD1U10V2KX-4GP C295 SC4D7U6D3V3KX-GP 220ohm 100MHz DY 83.BAT54.D81 1D05V_SM_CK C294 SC4D7U6D3V3KX-GP R202 0R0603-PAD 24mA 1D05V_RUN_PEGPLL 68.00217.521 C306 AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 3D3V_HV_S0 R376 0R0603-PAD R106 10R2J-2-GP 1D05V_S0 C692 SCD1U10V2KX-4GP L20 FCM1608CF-221T02-GP C752 SC4D7U6D3V3KX-GP C754 SC4D7U6D3V3KX-GP DY SC4D7U6D3V3KX-GP 1D05V_S0 C753 VCCA_PEG_PLL 1D05V_HV_S0 2 BAT54-5-GP SC1U10V3KX-3GP 1D05V_SM C755 VCCA_PEG_BG 50mAAA48 1D05V_RUN_PEGPLL 1D05V_S0 SC4D7U6D3V3KX-GP 2nd = 68.00248.061 AD48 C704 SCD1U10V2KX-4GP DY M_VCCA_MPLL C694 DY VCCA_PEG_BG 3D3V_S0 VSSA_LVDS D5 1 A LVDS VCCA_LVDS DY 1D05V_S0 J48 2 VCCA_MPLL 852mA D VCCA_HPLL U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 C621 SCD1U10V2KX-4GP VTT CRT PLL AE1 VCCA_DPLLB VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT C250 SC4D7U6D3V3KX-GP 1 AD1 M_VCCA_MPLL J47 R447 0R0603-PAD SC4D7U6D3V3KX-GP SC10U6D3V5MX-3GP FCM1608KF-1-GP L21 68.00206.041 1 2 R400 0R2J-2-GP 24mA C687 A VCCA_DPLLA L48 M_VCCA_HPLL 13.2mA UMA M_VCCA_HPLL 2nd = 68.00248.061 L6 M_VCCA_DPLLB VCCA_DAC_BG VSSA_DAC_BG F47 1D8V_TXLVDS_S0 1 C644 1D05V_SUS_MCH_PLL2 R156 0R0603-PAD DY SB 1208 VCCA_CRT_DAC VCCA_CRT_DAC A25 B25 M_VCCA_DPLLA R421 0R0603-PAD DY M_VCCA_DAC_BG R168 0R2J-2-GP C636 SC27P50V2JN-2-GP 2 DY FCM1608KF-1-GP L22 B B27 A26 DY M_VCCA_DPLLB C642 120ohm 100MHz OF 10 NB1H R379 0R2J-2-GP 1D5V_S0 480mA R430 0R0603-PAD SCD01U16V2KX-3GP 1 DY 2 R390 0R2J-2-GP UMA UMA DY SCD1U10V2KX-4GP C SC10U6D3V5MX-3GP 1D05V_S0 SCD1U10V2KX-4GP SC10U6D3V5MX-3GP 65mA C624 C207 UMA M_VCCA_DPLLA C622 5mA 1 R374 0R0603-PADC625 SCD1U10V2KX-4GP 2 65mA UMA 3D3V_S0_DAC 1D05V_S0 SCD1U10V2KX-4GP UMA R399 0R0603-PAD SCD01U16V2KX-3GP UMA UMA 3D3V_CRTDAC_S0 C617 UMA SC22U6D3V5MX-2GP BC1 74.09091.J3F R371 0R0603-PAD C206 C141 NC#4 G9091-330T11U-GP BC2 73mA R378 0R0603-PAD VOUT SC1U16V3ZY-GP SC1U16V3ZY-GP D VIN GND EN 1D05V_S0 3D3V_S0_DAC U13 3 3D3V_S0_DAC Imax = 300 mA UMA 5V_S0 Title Cantiga (5 of 6) Size Document Number Rev SB JV50 Date: Thursday, January 08, 2009 Sheet 10 of 60 AD+ C505 ISL88731_CCV 12 CSON NC#16 U32 SI4800BDY-T1 C517 C522 B 16 R295 GND VCOMP NC#5 ICOMP VREF NC#7 GND 10R2F-L-GP C9 SC10U25V6KX-1GP D D D D 17 C504 SCD22U50V3ZY-1GP VFB 15 PBATT_SENSE_R 100R2J-2-GP BATT_SENSE 48 29 C518 SC1U10V3KX-3GP 2 ISL88731_CCS ISL88731_VREF ICM ISL88731_CSIN 10KR2F-2-GP C515 SCD015U25V2KX-GP ISL88731_CSIP_R ISL88731_IINP 1KR2F-3-GP R303 C516 SCD01U50V2KX-1GP 1ISL88731_CCV1 R293 18 2 R300 B AD_IA SCD01U16V2KX-3GP C510 35 19 C10 SC10U25V6KX-1GP CSOP PGND ISL88731_CSIP NC#14 G S S S 14 CHG_AGND 1 D01R2512F-4-GP LGATE C512 R302 2 ISL88731_DLO C511 SC10U25V6KX-1GP 20 BT+_R L10 ISL88731_LX IND-10UH-119-GP SDA 20081104 1 C506 SCD1U50V3KX-GP C BAT54PT-GP 2 U33 SI4800BDY-T1 20081104 24 ISL88731_LX C521 D D D D CHG_AGND DY SC1U10V3KX-4GP SCL 23 2 G39 GAP-CLOSE-PWR-2U G40 GAP-CLOSE-PWR-2U 1 D15 ISL88731_DHI UGATE G41 GAP-CLOSE-PWR-2U 1 C508 SC10U25V6KX-1GP 25 21 R298 0R3-0-U-GP ISL88731_BST 2ISL88731_BST1 ISL88731_LDO ACOK PHASE 35,48 BAT_SDA ISL88731_CSSN_R ISL88731_VCC GAP-CLOSE-PWR-2U G37 10 35,48 BAT_SCL 27 26 CHRG_IN C509 SC1U10V3KX-4GP G S S S BOOT VDDP R299 4D7R3F-L-GP 2 13 CHG_AGND 20081104 G38 GAP-CLOSE-PWR-2U ISL88731_ACOK 20081028 2 ISL88731_CSSP CSSN VCC VDDSMB CHG_AGND CHG_AGND CSSP ACIN C507 SCD1U10V2KX-4GP DCIN 2 C514 SCD01U50V2KX-1GP R304 49K9R2F-L-GP 11 5V_S5 D SCD1U25V3KX-GP ISL88731_ACIN C 28 C519 SCD047U25V3KX-GP SC10U25V6KX-1GP 22 CHG_AGND R305 10R2J-2-GP C513 SC10U25V6KX-1GP U31 20081028 NC#1 C503 SC1U25V5KX-1GP CH521S-30PT-GP-U R307 215KR3F-1-GP C520 SCD1U25V3KX-GP ISL88731_DCIN K G42 GAP-CLOSE-PWR-2U R306 10R2J-2-GP ISL88731_ACOK A SCD1U25V3KX-GP R290 AD+_G_2 10KR2F-2-GP D16 D D D D R308 470KR2J-2-GP U34 S S S G AO4433-GP 100KR2J-1-GP Q22 2N7002EDW-GP 1ISL88731_CSSN 2 AD+ 1 10KR2J-3-GP 2 R288 1ISL88731_CSSP_R1 D01R2512F-4-GP G34 GAP-CLOSE-PWR-2U R289 AD+_G_1 G35 GAP-CLOSE-PWR-2U R291 AD+_G AO4433-GP DCBATOUT BT+ SCD1U25V3KX-GP D AD+_TO_SYS U30 S S S G D D D D ISL88731AHRZ-T-GP DY G36 GAP-CLOSE-PWR-2U 20081104 20081024 3D3V_AUX_S5 2090107 CHG_AGND R296 10KR2F-2-GP ISL88731_LDO AC_IN# R297 10KR2F-2-GP SB 1210 D 35 Q23 2N7002-11-GP ISL88731_ACOK_L G R292 0R0402-PAD ISL88731_ACOK JV50 A S A R294 15K8R3F-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title ISL88731A_Charger Size A3 Date: Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet 47 of 60 A B C D E Adaptor in to generate DCBATOUT DCIN1 GND TP173 TP172 AD+ AD_JK C R286 100KR2J-1-GP C R1 E R2 E Q20 B AD_OFF C500 SC1U50V5ZY-1-GP PDTA124EU-1-GP 35 D D D D B SB 1208 R287 200KR2F-L-GP Q21 AD_OFF#_JK U29 S S S G AO4407A-GP AD+_2 A 22.10037.G11 D14 P6SBMJ24APT-GP SCD1U50V3KX-GP DC-JACK150-GP C501 SCD1U50V3ZY-GP R1 EC28 R2 AFTE14P-GP AFTE14P-GP 1 K NP1 PDTC124EU-1-GP 3 BATTERY CONNECTOR SB 1204 BAT1 RN9 SRN33J-7-GP 35 BAT_IN# 35,47 BAT_SCL 35,47 BAT_SDA BAT_IN#_1 BATA_SCL_1 BATA_SDA_1 47 BATT_SENSE DY 1 EL2 GND GND GND GND BAT_IN CLK DAT BT+2 BT+1 For AFTE BATA_SDA_1 BATA_SCL_1 BAT_IN#_1 51 BATA_SDA_1 51 BATA_SCL_1 51 BAT_IN#_1 EC8 DY 1 DY 2 2 2 1 1 K A EL1 SC10P50V2JN-4GP DY EC9 SC10P50V2JN-4GP EL3 MLVS0402M04-GP EC10 MLVS0402M04-GP SB 1208 DY SC1000P50V3JN-GP EC30 SC1000P50V3JN-GP DY SCD1U50V3ZY-GP D1 MMPZ5232BPT-GP EC32 SCD1U50V3ZY-GP EC31 MLVS0402M04-GP BT+ DY R301 0R0402-PAD ALP-CON7-12-GP 20.81156.007 JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title AD/BATT CONN Size Document Number Rev SB JV50 Date: A B C Thursday, January 08, 2009 D Sheet 48 of E 60 DCBATOUT DCBATOUT_8202_VGA G74 GAP-CLOSE-PWR G75 GAP-CLOSE-PWR G77 DCBATOUT_8202_VGA R426 10R2F-L-GP DIS SB 1209 RT8202_DL_VGA GAP-CLOSE-PWR G64 GAP-CLOSE-PWR G62 GAP-CLOSE-PWR G61 2 1 1 DIS 2 DY DIS 2 DIS DY GND GND VDD RT8202APQW-GP PGND VOUT 17 NC#5 NC#14 2 SCD1U25V3ZY-1GP 10 GAP-CLOSE-PWR G60 20081024 GAP-CLOSE-PWR G58 GAP-CLOSE-PWR G57 RT8202_FB_VGA Vout=0.75*(1+Rh/Rl) GAP-CLOSE-PWR G56 R428 30KR2F-GP DIS DIS NV_VID0_R Q26 2N7002-7F-GP R435 NV_VID1 Q27 2N7002-7F-GP DIS R436 10KR2J-3-GP C740 SCD1U10V2KX-4GP DIS N10M-GE1 ALTV1 ALTV0 0 1 NV_VID0 G NVVDD_ALTV1 56 B GAP-CLOSE-PWR SB 1202 2 S DIS GAP-CLOSE-PWR G67 SB 1222 DIS G GAP-CLOSE-PWR G66 2 20081022 SB 1222 DIS NVVDD_ALTV0 56 D R427 47KR2F-GP D NV_VID1_R DIS 1 2 R429 59KR2F-GP B GAP-CLOSE-PWR G55 RT8202_FB_VGA DIS S R425 12KR2F-L-GP DIS C GAP-CLOSE-PWR G59 20081024 C709 SC47P50V2JN-3GP GAP-CLOSE-PWR G63 SE330U2VDM-L-GP OC FB SE330U2VDM-L-GP 14 VGA_CORE G65 TC14 EN/DEM DY U40 TC15 C684 U17 AOL1712-GP S S S G C 10KR2J-3-GP RT8202_BST_VGA_L DIS RT8202_DH_VGA 1R2F-GP RT8202_LX_VGA DIS RT8202_DL_VGA R406 RT8202_OC_VGA_L RT8202_LX_VGA RT8202_FB_VGA 4K75R2F-1-GP VGA_CORE_PWR DIS S S S G DIS 13 12 11 DIS VGA_CORE_PWR C708 SCD1U10V2KX-4GP 15 R416 BOOT UGATE PHASE LGATE DIS DIS Iomax=13A, OCP>20A VGA_CORE_PWR L19 IND-D56UH-12-GP RT8202_LX_VGA AOL1712-GP RT8202_EN_VGA TON PGOOD DIS D D D D 16 DIS RT8202_DH_VGA C668 2RT8202_LX_VGA SCD1U25V3KX-GP R412 DIS D D D D RT8202_PGOOD_VGA U45 VDDP DIS 0R0402-PAD-1-GP DIS 3D3V_S0 2 1 2 C710 SC100P50V2JN-3GP C685 SC1U10V3ZY-6GP C649 SCD1U50V3KX-GP DIS R420 S S S G C696 SC1KP50V2KX-1GP RT8202_BST_VGA DIS R422 10KR2F-2-GP 5V_S5 C665 SC10U25V6KX-1GP RT8202_TON_VGA C652 SC10U25V6KX-1GP CH521S-30-GP-U1 R418 1MR2F-GP 44,45 NVVDD_PGOOD U41 AOL1426-GP DIS SC10U25V6KX-1GP C711 SC1U10V3ZY-6GP D D D D D25 DIS DCBATOUT_8202_VGA 3D3V_S0 C655 SB 1202 RT8202_VDD_VGA GAP-CLOSE-PWR DIS D 5V_S5 DIS 2 DIS SE100U25VM-L1-GP D 5V_S5 GAP-CLOSE-PWR G76 TC17 10KR2J-3-GP C741 SCD1U10V2KX-4GP DIS Vout 0.90V 1.09V 1.2V 20081024 JV50 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Date: RT8202A_VGA CORE Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet 49 of 60 SB 1208 1D05V_S0 EC66 SCD1U50V3KX-GP EC67 SCD1U50V3KX-GP EC65 SCD1U50V3KX-GP EC64 SCD1U50V3KX-GP EC63 SCD1U50V3KX-GP EC62 SCD1U50V3KX-GP 2 EC61 SCD1U50V3KX-GP AD_JK DCBATOUT D D SB 1209 TC24 SE100U25VM-L1-GP 2 TC19 SE100U25VM-L1-GP 1 DCBATOUT C C -1 0109 B 1 ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX H10 HOLE HOLE355X355R111-S1-GP SPRING_GND24 SPRING-U3 SPRING_GND25 SPRING-43-GP-U JV50 A Wistron Corporation 34.40U07.001 34.40U07.001 DY 34.49U26.001 SPRING_GND23 SPRING-U3 DY 34.49U26.001 SPRING_GND22 SPRING-7 1 HOLE355X355R111-S1-GP H9 HOLE GND12 DY 34.49U26.001 H8 HOLE 34.4P901.001 SPRING_GND21 SPRING-7 SPRING_GND15 SPRING-7 DY 34.49U26.001 GND11 HOLE355X355R111-S1-GP GND10 SPRING_GND14 SPRING-7 34.41Y19.001 34.42Y01.011 HOLE355X355R111-S1-GP 1 SPRING_GND20 SPRING-12-GP-U GND9 GND7 MINICARD H7 HOLE ZZ.0HOLE.XXX 1 ZZ.0HOLE.XXX GND6 34.39S07.003 H6 HOLE 34.4Z003.001 34.4Z003.001 SPRING_GND19 SPRING-62-GP 34.4B312.002 MDC H5 HOLE HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP 1 GND5 SPRING_GND18 SPRING-58-GP 34.39S07.003 HOLE355X355R111-S1-GP GND4 SPRING_GND17 SPRING-62-GP 1 34.41Y19.001 1 SPRING_GND16 SPRING-12-GP-U A GND3 HOLE355X355R111-S1-GP GND2 HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP GND1 34.4H103.001 HOLE355X355R111-S1-GP 34.4Z003.001 34.4Z003.001 34.4H103.001 1 VGA H4 HOLE ZZ.0HOLE.XXX H3 HOLE ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX B H2 HOLE ZZ.0HOLE.XXX NB H1 HOLE CPU 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 34.15J03.001 Title SB 1208 -1 0109 SB 1208 -1 0109 EMI/Spring/Boss Size Document Number Date: Friday, January 09, 2009 JV50 Rev SB Sheet 50 of 60 A B Check test point D 3D3V_S0 TP214 AFTE14P-GP 28,29 SPKR_L+ TP7 AFTE14P-GP 3D3V_FP_S0 TP126 AFTE14P-GP TP213 AFTE14P-GP 28,29 SPKR_L- TP8 AFTE14P-GP 3D3V_FP_S0 TP125 AFTE14P-GP 3D3V_S5 TP210 AFTE14P-GP 37 USBPP6_1 TP128 AFTE14P-GP 5V_S5 TP209 AFTE14P-GP TP127 AFTE14P-GP TP142 AFTE14P-GP 35,37 FP_DETECT# TP132 AFTE14P-GP TP161 AFTE14P-GP FAN1 Conn Test Point keep on conector side 37 USBPN6_1 37 TP_LEFT TP124 AFTE14P-GP TP160 AFTE14P-GP 34 EMC2102_FAN_TACH_1 TP175 AFTE14P-GP 37 TP_RIGHT TP131 AFTE14P-GP TP112 AFTE14P-GP 34 EMC2102_FAN_DRIVE TP176 AFTE14P-GP TP136 AFTE14P-GP TP177 AFTE14P-GP TP134 AFTE14P-GP TP139 AFTE14P-GP 13,35 PM_PWRBTN# 4,12,39 H_PWRGD 35,42 S5_ENABLE H_CPURST# Test Point放 放 放 Dimm Door打 打打打打打打 KB1 Conn Test Point keep on connector side AMIC1 Conn Test Point keep on connector side 18,27 INT_MIC1 TP6 AFTE14P-GP TP5 AFTE14P-GP BT1 Conn Test Point keep on connector side 13,23 USBPN7 TP217 AFTE14P-GP 13,23 USBPP7 TP218 AFTE14P-GP TP220 AFTE14P-GP TP219 AFTE14P-GP 3D3V_BT_S0 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KCOL18 1 1 1 1 1 1 1 1 1 TP48 TP64 TP47 TP55 TP38 TP65 TP42 TP61 TP45 TP56 TP39 TP62 TP46 TP59 TP43 TP60 TP44 TP57 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP 35 35 35 35 35 35 35 35 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 1 1 1 1 TP40 TP52 TP35 TP53 TP36 TP37 TP54 TP51 TP66 AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP USB_OC#1 TP168 AFTE14P-GP TP163 AFTE14P-GP TP162 AFTE14P-GP TP164 AFTE14P-GP TP9 AFTE14P-GP TP10 AFTE14P-GP TP11 AFTE14P-GP TP12 AFTE14P-GP TP13 AFTE14P-GP TP19 AFTE14P-GP TP14 AFTE14P-GP TP15 AFTE14P-GP TP16 AFTE14P-GP TP17 AFTE14P-GP TP18 AFTE14P-GP AD_JK TPCN1 Conn Test Point keep on conector side 48 BATA_SDA_1 TP137 AFTE14P-GP 48 BATA_SCL_1 1 TP135 AFTE14P-GP 48 1 TP133 AFTE14P-GP 12,35,36 LPC_LFRAME# 7,13,25,31,32,33,35,36,52 PLT_RST1# TP165 AFTE14P-GP TP167 AFTE14P-GP TP169 AFTE14P-GP 5V_S5 TP170 AFTE14P-GP TPCN1 Conn Test Point keep on conector side 5V_S5 TP171 AFTE14P-GP AFTE14P-GP 3,36 TP123 AFTE14P-GP TP117 AFTE14P-GP TP143 AFTE14P-GP 5V_S0 TP77 AFTE14P-GP 5V_S0 TP93 AFTE14P-GP TP108 AFTE14P-GP PCLK_FWH DCIN1 Conn Test Point keep on connector side 1 AFTE14P-GP AFTE14P-GP 12,35,36 LPC_LAD3 TP21 TP41 12,35,36 LPC_LAD2 TP24 AFTE14P-GP 12,35,36 LPC_LAD1 USBPP2 TP63 USBPN2 1 38 13,24 SPKR_R- AFTE14P-GP 38 Volume_Down#_1 13,24 SPKR_R+ AFTE14P-GP Volume_Up#_1 TP58 TP138 AFTE14P-GP 28,29 TP67 TP140 AFTE14P-GP USBPP1 28,29 TP141 AFTE14P-GP 13,24 SPKR_R1 Conn Test Point keep on conector side AFTE14P-GP 38 PWR_CON_LED# USBPN1 AFTE14P-GP TP69 13,24 24,35 USB_PWR_EN# TP70 3D3V_S0 1 TP166 AFTE14P-GP 38 PWR_CON_BTN#_1 12,35,36 LPC_LAD0 3D3V_S0 USBCN1 Conn Test Point keep on connector side PSCN1 Conn Test Point keep on connector side DB1 Conn Test Point keep on conector side 13,24 E FPCN1 Conn Test Point keep on connector side 3D3V_AUX_S5 4,6 C SPKR_L1 Conn Test Point keep on conector side 37 TP_DATA 37 TP_CLK TP106 AFTE14P-GP TP91 AFTE14P-GP TP90 AFTE14P-GP 37 TP_RIGHT TP80 AFTE14P-GP 37 TP_LEFT TP79 AFTE14P-GP BAT_IN#_1 BT+ BT+ JV50 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title AFTE_TP Size A3 Date: A B Wistron Corporation C D Document Number Rev JV50 Thursday, January 08, 2009 SB Sheet E 51 of 60 3D3V_S0 C198 C203 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEX_TXP7 AM24 PEX_TXN7 AM25 PEG_TXP6 PEG_TXN6 PEG_RXP7 PEG_RXN7 AP23 AN23 PEG_TXP7 PEG_TXN7 PEG_RXP8 PEG_RXN8 AN25 AP25 DIS1 DIS1 C210 C216 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP8 PEG_TXN8 PEG_RXP9 PEG_RXN9 PEX_TXP8 AL25 PEX_TXN8 AK25 AR25 AR26 DIS1 DIS1 C221 C212 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP9 PEG_TXN9 PEX_TXP9 AL26 PEX_TXN9 AM26 AP26 AN26 B PEG_RXP10 PEG_RXN10 DIS1 DIS1 C231 C227 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP10 PEG_TXN10 PEG_RXP11 PEG_RXN11 AN28 AP28 DIS1 DIS1 C225 C230 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP11 PEG_TXN11 AR28 AR29 DIS1 DIS1 C238 C244 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEX_TXP13AM29 PEX_TXN13AM30 AP29 AN29 PEG_TXP13 PEG_TXN13 PEG_RXP14 PEG_RXN14 AN31 AP31 DIS1 DIS1 C248 C262 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEX_TXP14AM31 PEX_TXN14AM32 DIS1 DIS1 C260 C246 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEX_TXP15 AN32 PEX_TXN15AP32 PEG_TXP14 PEG_TXN14 PEG_RXP15 PEG_RXN15 AR34 AP34 2 1 2 2 1 2 1 2 1 1 2 2 SPDIF_GPU 27 1 M08B1 USE 72.24C16.Z01 That include Nvidia HDCP core TPAD14-GP 2 TP82 R111 36KR2F-GP DIS DIS DIS PEX_TX6 PEX_TX6# C111 DIS C572 OSC_SPREAD DIS R91 DIS 0R2J-2-GP VDD33 VDD33 VDD33 VDD33 VDD33 PEX_TX7 PEX_TX7# AE9 AD9 AF9 PLLVDD VID_PLLVDD SP_PLLVDD XTALSSIN D2 XTALSSIN XTALOUTBUFF B1 XTALIN R87 10KR2J-3-GP XTALOUT XTALOUTBUFF D1 B2 DIS N10M-GE1-B-U2-GP DY 3D3V_S0 PEX_RX6 PEX_RX6# 14 OF 16 VGA1N 1 C112 2 C581 C VIO_PLLVDD DIS C702 SC4D7U6D3V3KX-GP modify by NV PEX_RX5 PEX_RX5# TP75 TPAD14-GP R347 10KR2J-3-GP 71.0N10M.00U DIS X2 J10 J11 J12 J13 J9 C126 PEX_RX7 PEX_RX7# DIS PEX_TX8 PEX_TX8# C127 VGA_XIN1 DIS XTALIN R92 XTALOUT DY DIS 0R2J-2-GP XTAL-27MHZ-59-GP-U C94 SC20P50V2JN-1GP C103 SC20P50V2JN-1GP DY DY PEX_RX8 PEX_RX8# PEX_TX9 PEX_TX9# VDD_SENSE GND_SENSE PEX_RX9 PEX_RX9# AD20 AD19 NVVDD_SENSE NVGND_SENSE TP111 TPAD14-GP TP110 TPAD14-GP 1 PEX_RX10 PEX_RX10# L13 PEX_TX11 PEX_TX11# PEX_PLLVDD PEX_PLLVDD AG14 1D1V_S0 DIS PEX_RX11 PEX_RX11# C138 PEX_TX12 PEX_TX12# PEX_RX12 PEX_RX12# DIS PEX_TX13 PEX_TX13# C570 DIS C579 DIS IND-10NH-12-GP C558 DIS C701 DIS Logical Strap Bit Mapping Resistor Pull-up Pull-down 5Kohms 1000 0000 10Kohms 1001 0001 15Kohms 1010 0010 20Kohms 1011 0011 25Kohms 1100 0100 30Kohms 1101 0101 35Kohms 1110 0110 45Kohms 1111 0111 56 56 56 PEX_RX13 PEX_RX13# PEX_TX14 PEX_TX14# PEX_RFU1 PEX_RX14 PEX_RX14# PEX_RFU2 PEX_TERMP AG21 GPU_ROM_SI STRAP1 3GIO_PADCFG_LUT_ADR0=1 3GIO_PADCFG_LUT_ADR1=0 3GIO_PADCFG_LUT_ADR2=0 3GIO_PADCFG_LUT_ADR3=0 GPU_ROM_SO STRAP2 PCI_DEVID_0=0 PCI_DEVID_1=0 PCI_DEVID_2=1 PCI_DEVID_3=1 GPU_ROM_SCLK for Hynix 64X16 RAM_CFG_0=0 RAM_CFG_1=0 RAM_CFG_2=0 RAM_CFG_3=0 for Samsung 64X16 RAM_CFG_0=1 RAM_CFG_1=0 RAM_CFG_2=0 RAM_CFG_3=0 for Qimonda 64X16 RAM_CFG_0=0 RAM_CFG_1=1 RAM_CFG_2=0 RAM_CFG_3=0 TV_MODE_BIT0=1 TV_MODE_BIT1=0 TV_MODE_BIT2=0 XCLK_277 =1 PEX_PLL_EN_TERM100=0 SLOT_CLK_COFIG =1 SUB_VENDOR =0 PCI_DEVID_EXT =0 GPU_ROM_SI GPU_ROM_SO GPU_ROM_SCLK STRAP0 STRAP1 STRAP2 DY R118 R124 15KR2F-GP DIS R116 DIS R102 R81 1 DIS R349 R103 2KR2F-3-GP 15KR2F-GP DY R348 10KR2F-2-GP DY AP35 PEX_TESTMODE 15KR2F-GP 10KR2F-2-GP DY 45K3R2F-L-GP 3D3V_S0 DIS R100 2KR2F-3-GP DY 24K9R2F-L-GP DY PEX_TERMP R82 45K3R2F-L-GP DIS R350 2KR2F-3-GP 4K99R2F-L-GP SB 1215 R407 10KR2J-3-GP 71.0N10M.00U DIS USER_BIT0=1 USER_BIT1=1 USER_BIT2=1 USER_BIT3=1 DIS R127 3D3V_S0 AG20 R155 2K49R2F-GP TESTMODE B STRAP0 AG19 PEX_TX15 PEX_TX15# PEX_RX15 PEX_RX15# SB 1215 modify by NV and need to check NV mail PEX_TX10 PEX_TX10# N10M-GE1-B-U2-GP DIS A A A2 GND DIS modify by NV PEG_TXP15 PEG_TXN15 AR31 AR32 PEX_TX5 PEX_TX5# SC4D7U6D3V3KX-GP PEX_TXP12 AK29 PEX_TXN12 AL29 PEX_RX4 PEX_RX4# SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP A0 DIS A1 L16 BLM18AG221SN1D-GP SC1U6D3V2KX-GP C236 C240 PEX_TX4 PEX_TX4# 1D1V_S0 SCD1U10V2KX-5GP DIS1 DIS1 PEG_TXP12 PEG_TXN12 PEG_RXP13 PEG_RXN13 PEX_TXP11 AL28 PEX_TXN11AK28 PEX_RX3 PEX_RX3# SCD01U16V2KX-3GP PEG_RXP12 PEG_RXN12 PEX_TXP10AM27 PEX_TXN10AM28 VCC WP SCL SDA DIS1 DIS1 AR22 AR23 PEX_TXP6 AL23 PEX_TXN6 AM23 SCD1U16V2KX-3GP U9 SCD1U10V2KX-5GP SCD1U10V2KX-5GP BUFRST# PEG_RXP6 PEG_RXN6 RFU_GND RFU_GND STRAP_REF_MIOB DIS1 DIS1 C191 C200 PEG_TXP5 PEG_TXN5 DIS AK14 K9 PEX_TXP5 AL22 PEX_TXN5 AK22 Consign Part : CS.4AP72.003 C117 R121 DIS SCD1U10V2KX-5GP SCD1U10V2KX-5GP R120 D 71.0N10M.00U DIS SCD1U10V2KX-5GP C640 C641 PEX_TX3 PEX_TX3# SCD01U16V2KX-3GP DIS1 DIS1 DY 3D3V_S0 N10M-GE1-B-U2-GP AN22 AP22 PEX_RX2 PEX_RX2# PEG_RXP5 PEG_RXN5 PEX_TXP4 AM21 PEX_TXN4 AM22 HDCP_SDA DY SCD1U16V2KX-3GP DIS DIS A2 AB7 AD6 AF6 AG6 AJ5 AK15 AL7 D35 E35 E7 F7 H32 M7 P6 P7 R7 U7 V6 SCD1U10V2KX-5GP SCD1U10V2KX-5GP M9 R117 40K2R2F-GP SC4700P50V2KX-1GP C631 C637 HDCP_CLK G6 A4 C5 STRAP_REF_3V3 SCD1U10V2KX-4GP DIS1 DIS1 PEG_TXP4 PEG_TXN4 N9 SC1U6D3V2KX-GP AP20 AN20 F6 A5 SPDIF SC1U6D3V2KX-GP PEG_RXP4 PEG_RXN4 PEX_TXP3 AL20 PEX_TXN3 AM20 NC#A2 NC#AB7 NC#AD6 NC#AF6 NC#AG6 NC#AJ5 NC#AK15 NC#AL7 NC#D35 NC#E35 NC#E7 NC#F7 NC#H32 NC#M7 NC#P6 NC#P7 NC#R7 NC#U7 NC#V6 SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEX_TX2 PEX_TX2# 2 C173 C176 I2CH_SCL AT24C16BN-SHBY-B-GP PEX_RX1 PEX_RX1# DIS1 DIS1 PEG_TXP3 PEG_TXN3 GPU_ROM_SI GPU_ROM_SO GPU_ROM_SCLK DIS I2CH_SDA STRAP_MIOB AR19 AR20 GPU_ROM_CS# D3 C4 D4 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC R126 10KR2J-3-GP PEG_RXP3 PEG_RXN3 C PEX_TXP2 AL19 PEX_TXN2 AK19 DIS R115 40K2R2F-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP D7 D6 C7 B7 A7 HDA_SDATAIN2 10R2J-2-GP PEX_TX1 PEX_TX1# 2 C618 C628 1R125 PEX_RX0 PEX_RX0# DIS1 DIS1 PEG_TXP2 PEG_TXN2 DIS 12 ACZ_BITCLK_GPU 12 ACZ_RST#_GPU 12 ACZ_SDIN2 12 ACZ_SDATAOUT_GPU 12 ACZ_SYNC_GPU VCC HOLD# SCK SI AT25F512AN-10SU-GP C3 modify by NV BUFRST# PGOOD_OUT# PEG_RXP2 PEG_RXN2 AN19 AP19 DIS C178 STRAP_3V3 PEG_TXP1 PEG_TXN1 DIS C182 DIS AP17 AN17 DIS C149 PEX_TX0 PEX_TX0# PEX_TXP1 AM18 PEX_TXN1 AM19 DIS C133 SCD1U10V2KX-5GP SCD1U10V2KX-5GP DIS 1C195 CS# SO WP# GND 2 C160 C168 DIS C81 2K2R2J-2-GP DIS1 DIS1 PEX_REFCLK PEX_REFCLK# ROM_CS# 2K2R2J-2-GP PEX_TXP0 AL17 PEX_TXN0 AM17 DIS 1C118 C124 10KR2J-3-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP RFU#J26 RFU#J25 ROM_SI ROM_SO ROM_SCLK SC4D7U6D3V3KX-GP PEG_RXP1 PEG_RXN1 C159 C164 J26 J25 U10 13 OF 16 VGA1M SC4D7U6D3V3KX-GP AR16 AR17 DIS1 DIS1 PEX_TSTCLK_OUT PEX_TSTCLK_OUT# C132 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16 SC4D7U6D3V3KX-GP PEX_TSTCLK_OUT AJ17 PEX_TSTCLK_OUT# AJ18 200R2F-L-GP PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD SC22U6D3V5MX-2GP PEG_TXP0 PEG_TXN0 PEX_CLKREQ DIS R99 DIS VGA NB9P-GE2 Consign Part : CS.4AF71.005 C695 SC1U6D3V2KX-GP PEG_TXP[15 0] PEG_TXN[15 0] PEX_RST# DIS SCD47U6D3V2KX-GP PEG_RXP0 PEG_RXN0 AR13 R148 CLK_PCIE_PEG CLK_PCIE_PEG# PEG_RXP[15 0] PEG_RXN[15 0] AM16 SCD47U6D3V2KX-GP PEX_CLKREQ SCD1U10V2KX-5GP DIS DIS C161 1D1V_S0 SCD1U10V2KX-5GP TPAD14-GP TP186 DIS C202 SC4D7U6D3V3KX-GP PLT_RST1# DIS AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 C167 SC1U6D3V2KX-GP 7,13,25,31,32,33,35,36,51 C156 SCD1U10V2KX-5GP PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD D AK16 AK17 AK21 AK24 AK27 SCD1U10V2KX-5GP PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD R140 0R0402-PAD-1-GP PEX_RST# 1D1V_S0 OF 16 VGA1A DIS JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N10M(1/6)_PEG Size A2 Date: Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet 52 of 60 modify by NV 1 2 1 DIS 2 1 2 2 1 2 1 C184 DIS SC4D7U6D3V3KX-GP FBA_CMD_0 58 FBA_CMD_1 58,59 FBA_CMD_2 58 FBA_CMD_3 58,59 FBA_CMD_4 59 FBA_CMD_5 59 FBA_CMD_6 59 TP115 TPAD14-GP FBA_CMD_27 T32 T31 AC31 AC30 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# T30 FBA_DEBUG A0 A1 A3 A4 A5 CS1* CS0* WE* BA0 CS1* CS0* WE* BA0 CKE RST/ODT CKE RST/ODT A2 A12 RAS* A11 A10 BA1 A8 A9 A6 A12 RAS* A11 A10 BA1 A8 A9 A6 A5 A7 A4 CAS* A13 BA2 RFU0 RFU1 RFU2 A7 CAS* A13 BA2 RFU0 RFU1 RFU2 FBA_CMD_12 R191 DIS DIS F11 D10 D15 A16 D27 D28 D34 A34 E10 A10 D14 C14 E26 B26 D32 A32 58,59 D9 B10 E14 B14 F26 A26 D31 A31 FBVDD R179 G11 G12 G14 G15 G24 G25 G27 G28 60D4R2F-GP DIS 2 DIS DIS L7 1D1V_S0 D C FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 RFU_G11 RFU#_G12 RFU_G14 RFU#_G15 RFU_G24 RFU#_G25 RFU_G27 RFU#_G28 FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1# C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20 B E17 D17 D23 E23 modify by NV FBC_DEBUG FBAC_PLLAVDD FBAC_DLLAVDD N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27 G19 J19 J18 FB_PLLAVDD TP109 TPAD14-GP K27 FBCAL_PD_VDDQ L27 FBCAL_PU_GND M27 FBCAL_TERM_GND FBVDD BLM18AG221SN1D-GP DIS SC4D7U6D3V3KX-GP N10M-GE1-B-U2-GP 71.0N10M.00U DIS FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ C201 SC1U6D3V2KX-GP FB_VREF C223 1 FB_PLLAVDD AG27 AF27 FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 R190 FBA_CLK0 58 FBA_CLK0# 58 FBA_CLK1 59 FBA_CLK1# 59 DIS FBA_DEBUG FBA_CMD_11 32 63 A3 A0 A2 A1 10KR2J-3-GP FBA_CMD_8 58,59 FBA_CMD_9 58,59 FBA_CMD_10 58,59 FBA_CMD_11 58,59 FBA_CMD_12 58,59 FBA_CMD_13 59 FBA_CMD_14 58,59 FBA_CMD_15 58,59 FBA_CMD_16 58,59 FBA_CMD_17 58,59 FBA_CMD_18 58,59 FBA_CMD_19 58,59 FBA_CMD_20 58,59 FBA_CMD_21 58,59 FBA_CMD_22 58 FBA_CMD_23 58,59 FBA_CMD_24 58 FBA_CMD_25 58,59 1 FBA_CMD_7 CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 10KR2J-3-GP FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29 C209 1FB_VREF J27 DIS C162 SCD47U10V2MX-GP FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 SCD1U10V2KX-5GP TPAD14-GP TP113 DIS C183 31 FB_DLLAVDD FB_PLLAVDD modify by NV DIS C187 DIS SC4D7U6D3V3KX-GP RFU_P29 RFU#_R29 RFU_L29 RFU#_M29 RFU_AD29 RFU#_AE29 RFU_AG29 RFU#_AH29 C215 DIS D11 E11 F10 D8 F8 F9 E8 F12 B11 C13 A11 B8 A8 C8 C11 C10 D12 E13 F17 F15 F16 E16 F14 F13 D13 A13 B13 A14 C16 A17 B16 D16 D24 D26 E25 F25 F27 E28 F28 D29 A25 B25 D25 C26 C28 B28 A28 A29 E29 F29 D30 E31 C33 D33 F32 E32 B29 C29 B31 C31 B32 C32 B34 B35 FBVDD OF 16 VGA1C C150 SCD47U10V2MX-GP P29 R29 L29 M29 AD29 AE29 AG29 AH29 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 DIS DIS C219 SCD47U10V2MX-GP N32 L35 H31 G35 AD32 AC34 AJ31 AJ35 C153 DIS C211 SCD47U10V2MX-GP FBADQSN0 FBADQSN1 FBADQSN2 FBADQSN3 FBADQSN4 FBADQSN5 FBADQSN6 FBADQSN7 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 DIS C218 SCD1U10V2KX-5GP 58 58 58 58 59 59 59 59 N31 L34 J32 H35 AE31 AC33 AJ32 AJ34 C204 DIS DIS C154 SCD1U10V2KX-5GP FBADQSP0 FBADQSP1 FBADQSP2 FBADQSP3 FBADQSP4 FBADQSP5 FBADQSP6 FBADQSP7 DIS C217 SCD1U10V2KX-5GP 58 58 58 58 59 59 59 59 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 C163 SCD1U10V2KX-5GP FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7 J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22 SCD1U10V2KX-5GP B 58 58 58 58 59 59 59 59 P30 P32 J30 H34 AF32 AF35 AL32 AL34 FBVDD OF 16 FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ SCD1U10V2KX-5GP C FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 SCD1U10V2KX-5GP FBAD[32 63] R30 R32 P31 N30 L31 M32 M30 L30 P33 P34 N35 P35 N34 L33 L32 N33 K31 K30 G30 K32 G32 H30 F30 G31 H33 K35 K33 G34 K34 E33 E34 G33 AG30 AH31 AG32 AF31 AF30 AD30 AC32 AE30 AE32 AF33 AF34 AE35 AE33 AE34 AC35 AB32 AN33 AK32 AL33 AM33 AL31 AK30 AJ30 AH30 AM35 AH33 AH35 AH32 AH34 AM34 AL35 AJ33 SCD1U10V2KX-5GP 59 FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63 FBAD[0 31] VGA1B 58 D FBCAL_PD_VDDQ FBCAL_PU_GND FBCAL_TERM_GND DIS R173 30D1R2F-L-GP DIS R172 30D1R2F-L-GP DY R182 40D2R2F-GP N10M-GE1-B-U2-GP 71.0N10M.00U DIS A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N10M(2/6)_MEMORY Size A2 Date: Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet 53 of 60 AJ12 DACA_VREF AK12 DACA_RSET AK13 OF 16 DACA_VDD I2CA_SCL I2CA_SDA G1 G4 CRT_DDCCLK 19 CRT_DDCDATA 19 AM13 AL13 CRT_HSYNC CRT_VSYNC AM15 CRT_RED 19 AM14 CRT_GREEN 19 CRT_BLUE 19 D DACA_VREF DACA_RSET DACA_HSYNC DACA_VSYNC 19 19 R132 124R2F-U-GP DACA_RED DIS DACA_GREEN 2 1 C DACB_VDD AC6 DIS OF 16 VGA1E DACB_VDD DIS R136 150R2F-1-GP C R138 150R2F-1-GP DIS 150R2F-1-GP R141 N10M-GE1-B-U2-GP 71.0N10M.00U DIS DACA_BLUE AL14 DIS DACA_VDD 1 2 DIS C122 SCD1U10V2KX-5GP DIS C563 SCD1U10V2KX-5GP DIS C580 SC4700P50V2KX-1GP DIS SC1U6D3V2KX-GP C571 VGA1D modify by NV 1 D L15 BLM18AG221SN1D-GP 2 3D3V_S0 AC5 R107 10KR2J-3-GP AB6 DACB_VREF DACB_RSET DACB_CSYNC DIS DACB_RED DACB_GREEN DACB_BLUE AB5 AA4 AB4 Y4 N10M-GE1-B-U2-GP 71.0N10M.00U DIS B B OF 16 VGA1F AG7 DACC_VDD I2CB_SCL I2CB_SDA DACC_VDD AK6 AH7 G3 G2 NV_HDMI_CLK NV_HDMI_DAT 20 20 DACC_VREF DACC_RSET DACC_HSYNC DACC_VSYNC AM1 AM2 R109 10KR2J-3-GP DACC_RED DIS DACC_GREEN DACC_BLUE AK4 AL4 AJ4 N10M-GE1-B-U2-GP 71.0N10M.00U DIS A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N10M(3/6)_DAC Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 54 of 60 AM9 AM10 GPU_TXAOUT1- 18 GPU_TXAOUT1+ 18 GPU_TXAOUT2- 18 GPU_TXAOUT2+ 18 DIS IFPEF_PLLVDD AG9 AG10 IFPA_IOVDD IFPB_IOVDD IFPB_TXD4# IFPB_TXD4 AL10 AK10 AL11 AK11 TXAOUT3- TXAOUT3+1 TP101 TPAD14-GP TP99 TPAD14-GP AJ6 GPU_TXBCLK- 18 GPU_TXBCLK+ 18 AP8 AN8 AE7 GPU_TXBOUT0- 18 GPU_TXBOUT0+ 18 DIS IFPB_TXD5# IFPB_TXD5 IFPB_TXD6# IFPB_TXD6 IFPB_TXD7# IFPB_TXD7 AN10 AP10 GPU_TXBOUT1- 18 GPU_TXBOUT1+ 18 AR10 AR11 GPU_TXBOUT2- 18 GPU_TXBOUT2+ 18 AP11 AN11 TXBOUT3- TXBOUT3+1 IFPEF_IOVDD AD7 IFPEF_PLLVDD IFPEF_RSET DPL3_TXC#_AE5 DPL3_TXC_AE6 DPL2_TXD0#_AF5 DPL2_TXD0_AF4 IFPE_IOVDD DPL1_TXD1#_AG4 DPL1_TXD1_AH4 IFPF_IOVDD DPL0_TXD2#_AH5 DPL0_TXD2_AH6 AE5 AE6 AF5 AF4 AG4 AH4 AH5 AH6 R110 10KR2J-3-GP TP183 TPAD14-GP TP184 TPAD14-GP DIS N10M-GE1-B-U2-GP AUX#_AF2 AUX_AF3 71.0N10M.00U DIS C AD4 AE4 C101 D AUX#_AD4 AUX_AE4 AL1 AN13 AP13 OF 16 VGA1I R101 10KR2J-3-GP 1 2 DIS GPU_TXAOUT0- 18 GPU_TXAOUT0+ 18 IFPA_TXD3# IFPA_TXD3 SC470P50V2KX-3GP DIS C113 GPU_TXACLK- 18 GPU_TXACLK+ 18 AL8 AM8 IFPA_TXD2# IFPA_TXD2 IFPB_TXC# IFPB_TXC SC4700P50V2KX-1GP SC4D7U6D3V3KX-GP C96 IFPA_TXD1# IFPA_TXD1 DY IFPAB_IOVDD DIS IFPAB_PLLVDD IFPAB_RSET R128 1KR2F-3-GP L2 BLM18AG221SN1D-GP AM12 AM11 2 DIS IFPA_TXD0# IFPA_TXD0 DIS C573 SCD1U10V2KX-5GP C582 SC4700P50V2KX-1GP DIS SC4D7U6D3V3KX-GP C560 DIS FBVDD IFPAB_PLLVDD AK9 IFPAB_RSET AJ11 1 IFPA_TXC# IFPA_TXC modify by NV D OF 16 VGA1G FBVDD L12 BLM18AG221SN1D-GP AF2 AF3 C DPL3_TXC#_AH3 DPL3_TXC_AH2 DPL2_TXD0#_AH1 DPL2_TXD0_AJ1 DPL1_TXD1#_AJ2 DPL1_TXD1_AJ3 DPL0_TXD2#_AL3 DPL0_TXD2_AL2 OF 16 VGA1H AH3 AH2 AH1 AJ1 AJ2 AJ3 AL3 AL2 N10M-GE1-B-U2-GP AUX#_AN3 AUX_AP2 L1 BLM18AG221SN1D-GP AJ9 IFPCD_RSET AK7 AR2 AP1 IFPC_L3# IFPC_L3 DIS1 AM4 AM3 IFPC_L2# IFPC_L2 DIS1 AM5 AL5 IFPC_L1# IFPC_L1 DIS1 DPL0_TXD2#_AM6 DPL0_TXD2_AM7 AM6 AM7 IFPC_L0# IFPC_L0 DIS1 DIS IFPD_IOVDD C578 1 C569 2 2 2 RN56 SRN0J-10-GP-U HDMI_CLK- 7,20 HDMI_CLK+ 7,20 RN16 SRN0J-10-GP-U HDMI_DATA0- 7,20 HDMI_DATA0+ 7,20 RN17 SRN0J-10-GP-U HDMI_DATA1- 7,20 HDMI_DATA1+ 7,20 RN19 SRN0J-10-GP-U HDMI_DATA2- 7,20 HDMI_DATA2+ 7,20 B IFPC_IOVDD DIS AUX#_AN4 AUX_AP4 SC470P50V2KX-3GP AK8 SC4700P50V2KX-1GP DIS 71.0N10M.00U DIS TP179 TPAD14-GP TP178 TPAD14-GP DIS SC1U6D3V2KX-GP SC4D7U6D3V3KX-GP DIS C562 DPL3_TXC#_AR2 DPL3_TXC_AP1 DPL2_TXD0#_AM4 DPL2_TXD0_AM3 DPL1_TXD1#_AM5 DPL1_TXD1_AL5 AJ8 C106 IFPCD_RSET R112 1KR2F-3-GP L14 modify by NV BLM18AG221SN1D-GP IFPCD_IOVDD DIS IFPCD_PLLVDD 1 DIS IFPCD_PLLVDD 2 DIS C92 SC470P50V2KX-3GP 1D1V_S0 IFPC_AUX# IFPC_AUX modify by NV C97 SC4700P50V2KX-1GP DIS B SC1U6D3V2KX-GP C95 1 DIS 2 FBVDD AN3 AP2 DPL3_TXC#_AR4 DPL3_TXC_AR5 DPL2_TXD0#_AP5 DPL2_TXD0_AN5 DPL1_TXD1#_AN7 DPL1_TXD1_AP7 DPL0_TXD2#_AR7 DPL0_TXD2_AR8 AN4 AP4 AR4 AR5 AP5 AN5 AN7 AP7 AR7 AR8 N10M-GE1-B-U2-GP JV50 71.0N10M.00U DIS A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N10M(4/6) Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 55 of 60 RN54 I2CD_SCL I2CD_SDA 3D3V_S0 DIS R108 D modify by NV TPAD14-GP TP85 1MIOACAL_PD_VDDQ U5 1MIOACAL_PD_GND T5 MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ MIOA_VDDQ MIOAD0 MIOAD1 MIOAD2 MIOAD3 MIOAD4 MIOAD5 MIOAD6 MIOAD7 MIOAD8 MIOAD9 MIOAD10 MIOACAL_PD_VDDQ MIOAD11 MIOAD12 MIOACAL_PU_GND MIOAD13 MIOAD14 N5 NV_GPIO9 10KR2J-3-GP D B4 TPAD14-GP TP94 1VGA_THERMDC TPAD14-GP TP100 1VGA_THERMDA THERMDN DY 1 1 1 71.0N10M.00U DIS TP103 TP104 TP105 TP107 TP102 DIS TPAD14-GP TP96 TPAD14-GP TP89 B 11 OF 16 VGA1K SCD1U10V2KX-4GP C114 AA9 AB9 W9 Y9 1MIOBCAL_PD_VDDQ AA7 1MIOBCAL_PD_GND AA6 AF1 MIOB_VDDQ MIOB_VDDQ MIOB_VDDQ MIOB_VDDQ MIOBCAL_PD_VDDQ MIOBCAL_PU_GND MIOB_VREF R131 10KR2J-3-GP MIOBD0 MIOBD1 MIOBD2 MIOBD3 MIOBD4 MIOBD5 MIOBD6 MIOBD7 MIOBD8 MIOBD9 MIOBD10 MIOBD11 MIOBD12 MIOBD13 MIOBD14 MIOBD15 MIOBD16 MIOBD17 MIOB_CTL3 MIOB_HSYNC MIOB_VSYNC MIOB_DE MIOB_CLKOUT MIOB_CLKOUT# MIOB_CLKIN Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 W5 W7 V7 DIS THERMDP I2CC_SCL I2CC_SDA I2CD_SCL I2CD_SDA I2CE_SCL I2CE_SDA GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 JTAG_TCK AP14 JTAG_TCK GPIO9 JTAG_TMS AR14 JTAG_TMS GPIO10 JTAG_TDI AN14 JTAG_TDI GPIO11 JTAG_TDO AN16 JTAG_TDO GPIO12 JTAG_TRST# AP16 JTAG_TRST# GPIO13 GPIO14 GPIO15 R130 GPIO16 10KR2J-3-GP GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 SWAP_RDY_A/GPIO22 DIS STEREO/GPIO23 R4 T4 N4 TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP I2CS_SCL I2CS_SDA P5 N3 L3 N2 N10M-GE1-B-U2-GP 3D3V_S0 12 OF 16 E2 E1 SMBC_Therm 34,35 SMBD_Therm 34,35 C110 B5 C 3D3V_S0 SRN10KJ-5-GP DIS SC2200P50V2KX-2GP MIOA_CLKOUT MIOA_CLKOUT# MIOA_CLKIN DIS VGA1L MIOA_VREF MIOA_CTL3 MIOA_HSYNC MIOA_VSYNC MIOA_DE I2CE_SCL I2CE_SDA 3D3V_S0 DIS R122 N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 TPAD14-GP TP84 NV_GPIO8 10KR2J-3-GP 10 OF 16 VGA1J P9 R9 T9 U9 3D3V_S0 SRN10KJ-5-GP RN55 E3 E4 F4 G5 D5 E5 I2CD_SCL I2CD_SDA I2CE_SCL I2CE_SDA K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 LCD_EDID_CLK LCD_EDID_DAT 18 18 HDMI_A_HPD 20 LCDVDD_ON 18 BLON_IN 35 NVVDD_ALTV0 49 NVVDD_ALTV1 49 NVVDD_ALTV0 NVVDD_ALTV1 NV_GPIO8 NV_GPIO9 MEM_VREF_CTRL1 TP83 C TPAD14-GP modify by NV N10M-GE1-B-U2-GP 71.0N10M.00U DIS STRAP0 STRAP1 STRAP2 modify by NV STRAP0 52 STRAP1 52 STRAP2 52 B W3 W1 W2 Y5 V4 W4 AE1 N10M-GE1-B-U2-GP 71.0N10M.00U DIS A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N10M(5/6)_MIO/ GPIO Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 56 of 60 VGA1O15 OF 16 VGA_CORE 1 2 1 2 C120 DIS DIS C172 B C166 SC4D7U10V3KX-GP DIS DIS C180 SCD47U6D3V2KX-GP C131 SC4D7U10V3KX-GP DIS C152 SCD47U6D3V2KX-GP 71.0N10M.00U DIS SC4D7U10V3KX-GP N10M-GE1-B-U2-GP C197 DIS SCD47U6D3V2KX-GP DIS C144 SCD47U6D3V2KX-GP DIS 1 C199 2 DIS SCD47U6D3V2KX-GP DIS C C129 DIS C192 DIS 2 C142 1 2 DIS SCD1U10V2KX-5GP C121 DIS SCD47U6D3V2KX-GP C125 DIS C171 SCD1U10V2KX-5GP DIS C145 SCD47U6D3V2KX-GP DIS DIS C179 C123 DIS SCD1U10V2KX-5GP C193 DIS SCD1U10V2KX-5GP C148 DIS DIS C134 SCD1U10V2KX-5GP DIS C181 SCD1U10V2KX-5GP C155 VGA_CORE SCD47U6D3V2KX-GP P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 SCD47U6D3V2KX-GP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SCD1U10V2KX-5GP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VGA1P 16 OF 16 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 VGA_CORE SCD1U10V2KX-5GP A D SCD47U6D3V2KX-GP B E15 E18 E24 E27 E30 E6 E9 F2 F31 F34 F5 J2 J31 J34 J5 L9 M11 M13 M15 M17 M19 M2 M21 M23 M25 M31 M34 M5 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R31 R34 R5 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V12 V14 V16 V18 V2 V20 V22 V24 V31 V5 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 SC1U6D3V3KX-2GP C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SC1U6D3V3KX-2GP AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AA5 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD11 AD13 AD15 AD17 AD2 AD21 AD23 AD25 AD31 AD34 AD5 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG31 AG34 AG5 AK2 AK31 AK34 AK5 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AL6 AL9 AN2 AN34 AP12 AP15 AP18 AP21 AP24 AP27 AP3 AP30 AP33 AP6 AP9 B12 B15 B21 B24 B27 B3 B30 B33 B6 B9 C2 C34 E12 A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C N10M-GE1-B-U2-GP 71.0N10M.00U DIS Title N10M(6/6)_POWER Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 57 of 60 K4N1G164QQ-HC20-GP 1 2 1 2 1 2 1 2 VSS VSS VSS VSS VSS DIS DY DIS C372 DIS 2 C312 DIS C366 DIS C338 DIS C322 C303 A3 E3 J3 N1 P9 DIS C318 1 DY C336 C301 NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 C334 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VREF DIS C FBVDD UDQS UDQS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C339 LDQS LDQS# C316 ODT DY J1 J7 FBVDD VDDL VSSDL DIS K4N1G164QQ-HC20-GP DIS B DIS SCD1U10V2KX-5GP FBA_CMD_27 53,59 FBA_CMD_27 J2 A2 E2 L1 R3 R7 R8 LDM UDM A1 E1 J9 M9 R1 SCD1U10V2KX-5GP DIS SCD01U50V2KX-1GP A3 E3 J3 N1 P9 CAS# VDD VDD VDD VDD VDD B7 A8 C355 FBA_VREF12 RAS# FBADQSP0 FBADQSN0 F7 E8 WE# 53 53 K9 CS# A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 FBADQSP1 FBADQSN1 CKE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ FBA_CMD_12 53,59 FBA_CMD_12 53 53 L7 F3 B3 FBADQM1 FBADQM0 DIS D C315 FBVDD CK# CK 2 53 53 DY C358 SC1U6D3V2KX-GP DIS FBA_CMD_25 53,59 FBA_CMD_25 C314 DIS SCD1U10V2KX-5GP A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 C319 DIS DIS C364 SCD1U10V2KX-5GP VSS VSS VSS VSS VSS C299 C376 C357 SCD1U10V2KX-5GP NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 K7 DIS DIS SCD1U10V2KX-5GP VREF K3 DIS C330 C346 SCD1U10V2KX-5GP FBA_CMD_27 53,59 FBA_CMD_27 J2 A2 E2 L1 R3 R7 R8 UDQS UDQS# VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ FBA_CMD_9 FBA_CMD_15 53,59 FBA_CMD_9 53,59 FBA_CMD_15 DIS ODT LDQS LDQS# FBVDD C343 DIS SCD1U10V2KX-5GP DIS SCD01U50V2KX-1GP J1 J7 L8 DIS C332 SC1U6D3V2KX-GP B7 A8 C356 FBA_VREF12 VDDL VSSDL FBA_CMD_8 53,59 FBA_CMD_8 53 SC1U6D3V2KX-GP FBADQSP2 FBADQSN2 F7 E8 LDM UDM K2 FBAD[0 31] FBAD6 FBAD0 FBAD4 FBAD1 FBAD5 FBAD3 FBAD2 FBAD7 FBAD13 FBAD11 FBAD14 FBAD8 FBAD12 FBAD10 FBAD9 FBAD15 SCD047U16V2KX-1-GP 53 53 K9 CAS# VDD VDD VDD VDD VDD FBA_CMD_11 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 SCD047U16V2KX-1-GP FBADQSP3 FBADQSN3 RAS# A1 E1 J9 M9 R1 FBA_CLK0# FBA_CLK0 53,59 FBA_CMD_11 SCD047U16V2KX-1-GP FBA_CMD_12 53,59 FBA_CMD_12 53 53 L7 F3 B3 FBADQM3 FBADQM2 WE# 53 53 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 SC1U6D3V2KX-GP K7 FBA_CMD_25 53,59 FBA_CMD_25 53 53 K3 CS# A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 SCD047U16V2KX-1-GP C FBA_CMD_9 FBA_CMD_15 CKE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ BA0 BA1 SC1U6D3V2KX-GP 53,59 FBA_CMD_15 L8 FBA_CMD_14 R2 FBA_CMD_16 P7 FBA_CMD_17 M2 FBA_CMD_20 P3 FBA_CMD_19 P8 FBA_CMD_23 P2 FBA_CMD_21 N7 FBA_CMD_22 N3 FBA_CMD_24 N8 FBA_CMD_0 N2 FBA_CMD_2 M7 FBA_CMD_3 M3 FBA_CMD_1 M8 R206 DY 475R2F-L1-GP K8 J8 53,59 FBA_CMD_14 53,59 FBA_CMD_16 53,59 FBA_CMD_17 53,59 FBA_CMD_20 53,59 FBA_CMD_19 53,59 FBA_CMD_23 53,59 FBA_CMD_21 53 FBA_CMD_22 53 FBA_CMD_24 53 FBA_CMD_0 53 FBA_CMD_2 53,59 FBA_CMD_3 53,59 FBA_CMD_1 FBVDD CK# CK L2 L3 SC1U6D3V2KX-GP 53,59 FBA_CMD_9 FBA_CMD_8 FBA_CMD_10 FBA_CMD_18 53,59 FBA_CMD_10 53,59 FBA_CMD_18 SC1U6D3V2KX-GP 53,59 FBA_CMD_8 K2 FBRAM2 53 SC1U6D3V2KX-GP 53,59 FBA_CMD_11 FBA_CMD_11 FBAD[0 31] FBAD23 FBAD21 FBAD17 FBAD16 FBAD18 FBAD20 FBAD19 FBAD22 FBAD27 FBAD25 FBAD30 FBAD26 FBAD24 FBAD29 FBAD28 FBAD31 SC1U6D3V2KX-GP FBA_CLK0# FBA_CLK0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 SC1U6D3V2KX-GP 53 53 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 SC1U6D3V2KX-GP FBA_CMD_14 R2 FBA_CMD_16 P7 FBA_CMD_17 M2 FBA_CMD_20 P3 FBA_CMD_19 P8 FBA_CMD_23 P2 FBA_CMD_21 N7 FBA_CMD_22 N3 FBA_CMD_24 N8 FBA_CMD_0 N2 FBA_CMD_2 M7 FBA_CMD_3 M3 FBA_CMD_1 M8 R208 DIS2 475R2F-L1-GP K8 J8 53,59 FBA_CMD_14 53,59 FBA_CMD_16 53,59 FBA_CMD_17 53,59 FBA_CMD_20 53,59 FBA_CMD_19 53,59 FBA_CMD_23 53,59 FBA_CMD_21 53 FBA_CMD_22 53 FBA_CMD_24 53 FBA_CMD_0 53 FBA_CMD_2 53,59 FBA_CMD_3 53,59 FBA_CMD_1 BA0 BA1 SC1U6D3V2KX-GP D L2 L3 SC4D7U6D3V3KX-GP C307 FBRAM1 FBA_CMD_10 FBA_CMD_18 53,59 FBA_CMD_10 53,59 FBA_CMD_18 FBVDD DIS B modify by NV FBVDD R205 1K05R2F-GP DIS A C331 SCD01U50V2KX-1GP A JV50 DIS DIS FBA_VREF12 R204 1K05R2F-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM(1/2) Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 58 of 60 FBVDD K4N1G164QQ-HC20-GP DIS DIS 1 2 1 2 1 2 1 2 2 A3 E3 J3 N1 P9 C351 DIS B DIS C373 DY DIS C362 DIS C337 DIS C370 DIS C325 C353 C326 DIS DY C304 FBVDD 2 K4N1G164QQ-HC20-GP A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 C297 DIS SCD1U10V2KX-5GP VSS VSS VSS VSS VSS DIS C SCD1U10V2KX-5GP NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 C321 FBA_CMD_27 53,58 FBA_CMD_27 VREF C328 SCD1U10V2KX-5GP A3 E3 J3 N1 P9 J2 A2 E2 L1 R3 R7 R8 DIS C761 FBA_VREF34 SCD01U50V2KX-1GP D SCD1U10V2KX-5GP DIS UDQS UDQS# DIS B7 A8 C311 FBADQSP6 FBADQSN6 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C342 53 53 ODT LDQS LDQS# DY F7 E8 DIS J1 J7 SCD1U10V2KX-5GP VSS VSS VSS VSS VSS FBADQSP7 FBADQSN7 C341 DIS FBVDD A1 E1 J9 M9 R1 SCD1U10V2KX-5GP NC#A2 NC#E2 BA2 NC#R3 NC#R7 NC#R8 53 53 VDDL VSSDL DIS C368 SCD1U10V2KX-5GP FBA_CMD_27 VREF K9 LDM UDM C345 SCD1U10V2KX-5GP 53,58 FBA_CMD_27 J2 A2 E2 L1 R3 R7 R8 FBA_CMD_12 53,58 FBA_CMD_12 CAS# VDD VDD VDD VDD VDD SC1U6D3V2KX-GP C354 FBA_VREF34 SCD01U50V2KX-1GP F3 B3 FBADQM7 FBADQM6 RAS# SC1U6D3V2KX-GP DIS UDQS UDQS# 53 53 WE# DIS B7 A8 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 53,58 FBA_CMD_25 L7 FBADQSP4 FBADQSN4 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C352 FBA_CMD_25 CS# C371 53 53 LDQS LDQS# DIS K7 F7 E8 ODT C300 K3 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 DIS DIS FBADQSP5 FBADQSN5 DIS J1 J7 FBA_CMD_9 FBA_CMD_15 CKE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C344 53 53 VDDL VSSDL 53,58 FBA_CMD_9 53,58 FBA_CMD_15 DIS C333 K9 LDM UDM FBVDD A1 E1 J9 M9 R1 L8 C317 DIS FBA_CMD_12 53,58 FBA_CMD_12 CAS# VDD VDD VDD VDD VDD K2 FBA_CMD_8 DIS C310 SC1U6D3V2KX-GP F3 B3 FBADQM5 FBADQM4 RAS# FBA_CMD_11 C296 FBVDD CK# CK 53 SC1U6D3V2KX-GP L7 WE# 53,58 FBA_CMD_8 FBAD[32 63] FBAD49 FBAD55 FBAD53 FBAD48 FBAD51 FBAD52 FBAD54 FBAD50 FBAD59 FBAD62 FBAD58 FBAD61 FBAD63 FBAD57 FBAD56 FBAD60 SC1U6D3V2KX-GP FBA_CMD_25 CS# 53,58 FBA_CMD_11 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 SC1U6D3V2KX-GP K7 FBA_CLK1# FBA_CLK1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 SCD047U16V2KX-1-GP K3 53 53 BA0 BA1 SCD047U16V2KX-1-GP FBA_CMD_9 FBA_CMD_15 CKE A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 SCD047U16V2KX-1-GP 53 53 L8 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ SCD047U16V2KX-1-GP 53,58 FBA_CMD_25 C K2 FBA_CMD_8 FBA_CMD_14 R2 FBA_CMD_16 P7 FBA_CMD_17 M2 FBA_CMD_20 P3 FBA_CMD_19 P8 FBA_CMD_23 P2 FBA_CMD_21 N7 FBA_CMD_6 N3 FBA_CMD_5 N8 FBA_CMD_4 N2 FBA_CMD_13 M7 FBA_CMD_3 M3 FBA_CMD_1 M8 R210 DY 475R2F-L1-GP K8 J8 53,58 FBA_CMD_14 53,58 FBA_CMD_16 53,58 FBA_CMD_17 53,58 FBA_CMD_20 53,58 FBA_CMD_19 53,58 FBA_CMD_23 53,58 FBA_CMD_21 53 FBA_CMD_6 53 FBA_CMD_5 53 FBA_CMD_4 53 FBA_CMD_13 53,58 FBA_CMD_3 53,58 FBA_CMD_1 FBVDD CK# CK L2 L3 SC1U6D3V2KX-GP 53,58 FBA_CMD_9 53,58 FBA_CMD_15 FBA_CMD_11 FBA_CMD_10 FBA_CMD_18 53,58 FBA_CMD_10 53,58 FBA_CMD_18 SC1U6D3V2KX-GP 53,58 FBA_CMD_8 FBRAM4 53 SC1U6D3V2KX-GP 53,58 FBA_CMD_11 FBAD[32 63] FBAD37 FBAD33 FBAD38 FBAD32 FBAD35 FBAD36 FBAD34 FBAD39 FBAD46 FBAD41 FBAD47 FBAD40 FBAD45 FBAD44 FBAD42 FBAD43 SC1U6D3V2KX-GP FBA_CLK1# FBA_CLK1 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 SC1U6D3V2KX-GP 53 53 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 SC1U6D3V2KX-GP FBA_CMD_14 R2 FBA_CMD_16 P7 FBA_CMD_17 M2 FBA_CMD_20 P3 FBA_CMD_19 P8 FBA_CMD_23 P2 FBA_CMD_21 N7 FBA_CMD_6 N3 FBA_CMD_5 N8 FBA_CMD_4 N2 FBA_CMD_13 M7 FBA_CMD_3 M3 FBA_CMD_1 M8 R209 DIS 475R2F-L1-GP K8 J8 53,58 FBA_CMD_14 53,58 FBA_CMD_16 53,58 FBA_CMD_17 53,58 FBA_CMD_20 53,58 FBA_CMD_19 53,58 FBA_CMD_23 53,58 FBA_CMD_21 53 FBA_CMD_6 53 FBA_CMD_5 53 FBA_CMD_4 53 FBA_CMD_13 53,58 FBA_CMD_3 53,58 FBA_CMD_1 BA0 BA1 SC4D7U6D3V3KX-GP D L2 L3 FBRAM3 FBA_CMD_10 FBA_CMD_18 53,58 FBA_CMD_10 53,58 FBA_CMD_18 B modify by NV FBVDD SB All Component for NB9P-GE2 R449 1K05R2F-GP DIS A C762 SCD01U50V2KX-1GP A JV50 DIS DIS FBA_VREF34 R207 1K05R2F-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM(2/2) Size A3 Date: Document Number Thursday, January 08, 2009 Rev JV50 SB Sheet 59 of 60 SB SC -1 SB 12/02 Page3: change C452 C453 from 27P to 33P by vendor's request Page20: swap HDMI signals for routing Page33: add C872 33P for SIV Page28: change U53 pin22 from AUD_HP1_EN to AMP_MUTE#_R Page29: change SPKR_R1 SPKR_L1 from 20.F1396.002 to 20.F1214.002 by CE's request Page48: change BAT1 from 20.81094.007 to 20.81156.007 Page18: change LCD1 from 20.F1296.040 to 20.F1230.040 by CE's request Page22: change ODD1 from 62.10065.541 to 62.10065.751 Page24: change USBCN1 from 20.F1290.015 to 20.F1035.015 by CE's request D 12/04 Page24: change U47 from 74.00545.A79 to 74.00547.A79 Page22: change R231 R247 from 0ohm resistor to 0ohm pad Page38: change PSCN1 from 20.K0356.006 to 20.K0382.006 by CE's request Page18: change AMIC1 from 20.F1396.002 to 20.F1214.002 by CE's request D 12/05 Page25: change R39 R53 R21 R31 R22 R35 R28 from 0ohm resistor to 0ohm pad Page3: add R554 and change U24 pin16 from 3D3V_S0 to 3D3V_VDD48_S0 Page3: change C457 C450 C416 C430 C418 from mount to DY and change C456 from DY to mount Page46: change L23 from 68.R8210.10V to 68.1R01A.20B and change U43 from 84.04812.A37 to 84.04168.037 by power team's request Page7: change R192 R195 from 0ohm resistor to 0ohm pad and add R555 RN82 RN83 RN84 RN85 for reflection Page41: change R344 from 2K87 to 3K16 and change C586 from 0.47u to 0.1u by power team's request Page9: change C275 from UMA to DY and change C349 from mount to DY Page10: change C243 C758 from mount to DY and change R167 R398 from DIS to DY Page41: change U35 U39 from 84.01426.037 to 84.12003.A37 and change U6 U7 U36 U38 from 84.01712.037 to 84.57N03.A37 by power team's request Page13: change R216 from 0ohm resistor to 0ohm pad Page14: change C413 C252 C703 C392 C707 C734 from mount to DY Page45: change R457 from 11K to 3K48 and change TC23 from 390u to 220u by power team's request Page17: change C426 C429 from mount to DY Page18: change C7 C499 from mount to DY and change R1 from mount to DIS and change R3 from DY to UMA Page20: add RN86 for DIS HDMI SMbus 12/08 Page26: change EC7 from DY to mount EMI's request Page25: change R45 from 0ohm resistor to 0ohm pad Page48: change EC28 EC30 EC31 EC32 from DY to mount EMI's request Page27: change R523 from 0ohm resistor to 0ohm pad Page31: change EC51 EC52 EC55 EC57 from 0.1u DY to 22p mount EMI's request Page7: add R556 pull-low DY for A1 NB Page5: change C79 C80 from DY to mount EMI's request Page28: change AGND & GND and change R509 from 0ohm resistor to 0ohm pad Page46: change C659 from DY to GFX EMI's request Page28: change C795 C790 C792 from mount to DY and change R480 R479 from 0ohm to 6K2 and 8K2 Page50: change SPRING_GND16-SPRING_GND20 from DY to mount EMI's request Page28: combine C801 C802 two 1u to C801 4.7u Page50: add EC61-EC67 0.1u by EMI's request Page28: delete C815 C814 C809 R500 R503 R513 R507 R502 R508 D31 U56 and change U55 to 84.2N702.E31 Page20: change R313 R314 from 10K 100K to 18K 47K by NV's request Page28: change R474 from DY to mount and change R475 from mount to DY for 10dB Page35: change U14 pin83 RN65 pin2 from SHBM to DBC_EN by annie's request Page29: add L29 L30 L31 L32 L33 L34 for ESD Page18: change LCD1 pin35 from NC to DBC_EN by annie's request Page31: change R463 R464 R471 R467 R466 R460 R459 R494 R484 R493 R486 R485 R488 R489 R490 R492 R491 R487 from 0ohm resistor to 0ohm pad Page20: add ER1-ER8 0ohm pad by EMI's request C C Page10: change C636 from 1000p DY to 27p mount by RF's request Page32: change C487 C477 from mount to DY and change R269 from 0ohm resistor to 0ohm pad Page12: change C385 C386 from 10p to 7p by vendor's request 12/09 Page49: change R406 from 6K2 to 4K75 by power team's request Page35: change C136 C169 from 15p to 7p by vendor's request Page46: change TC16 from mount to GFX Page33: change R15 R29 R34 from 0ohm resistor to 0ohm pad and change C542 from mount to DY Page50: add TC19 TC24 100u Page34: change C42 from mount to DY B Page36: change DB1 from mount to DY Page46: change C656 C653 from 10u to 4.7u and change C653 from GFX to DY Page38: add Q35 PWR_LED7 PWR_LED8 and change RN4 from 4P2R to 8P4R and change PWR_LED5 PWR_LED6 from 83.01221.I70 to 83.00193.A70 for LED type Page42: change C856 C857 C851 C850 from 10u to 4.7u and change C857 C850 from mount to DY Page41: change TC5 from DY to mount Page39: change U66 pin1 from CPUCORE_ON to 1D5V_PWRGD and change D13 pin1 from S5_ENABLE to 3V/5V_EN Page5: change C553 C538 C552 C539 C547 C536 C548 C537 from DY to mount Page40: update power sequence logic Page17: change C426 C428 C429 from 10u to 4.7u and change C429 from DY to mount Page41: change G43-G50 from open gap to close gap and change R328 R352 R353 R317 R316 R319-R325 from 0ohm resistor to 0ohm pad Page16: change C440-C442 C463-C465 from 10u to 4.7u and change C440 from DY to mount and change C464 from DY to mount Page42: change R532 R545 R552 from 0ohm resistor to 0ohm pad and change G118-G128 G130-G140 from open gap to close gap Page20: change HDMI from 62.10078.161 to 62.10078.171 by CE's request Page43: change R246 R233 from 0ohm resistor to 0ohm pad and change G5-G16 G18-G33 from open gap to close gap Page24: change USBCN1 from 20.F1035.015 to 20.F1290.015 by CE's request Page43: change R246 pin2 from CPUCORE_ON to 1D5V_PWRGD and add R500 pull-high 10K 3D3V_S5 12/10 Page46: add C873 33p GFX by RF's request Page45: change G100-G109 from open gap to close gap A Page43: add C874 C875 33p by RF's request Page46: change R157 R187 from 0ohm resistor to 0ohm pad and change G68-G73 G86 G87 G89 G90 G92 G93 G95 G96 G99 from open gap to close gap A Page20: swap U8 pin13 14 47 48 Page33: change R16 from DY to mount Page46: delete TC19 and change TC20 from DY to GFX Page47: change R292 from 0ohm resistor to 0ohm pad Page49: change G55-G67 G74-G77 from open gap to close gap JV50 Wistron Corporation Page29: change RN75 from 47ohm to 75ohm 12/11 Page33: change MINI2 pin 51 from 5V_S5_MIN1 to 5V_S5_MIN2 Page28: change C804 C807 from 4.7u to 1u 25V X5R Page45: delete TC24 12/15 Page52: change VRAM strap R350 Page19: delete R104 R129 B Page41: change C528 C529 530 C588 C597 C604 from 10u to 4.7u and change C528 C588 from mount to DY Page35: change C615 C626 C638 R395 from mount to DY and change R394 from DY to mount for PCB version 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title HISTORY Size A2 Date: Document Number Rev SB JV50 Thursday, January 08, 2009 Sheet 60 of 60 SB SC -1 SB 12/22 Page49: change R427 from 30K 47K and R428 from 47K to 30K SC 12/22 Page42: modify by power team's request Page35: change R372 R395 from DY to mount and change R373 R394 from mount to DY D D -1 01/06 Page17: change C400 from mount to DY and change C399 from DY to mount Page30: change R267 from 39R to 0ohm pad Page38: delete RN7 and add Q36 Q37 Page25: change U3 pin 38 52 from LAN_AVDD to TP and change U3 pin 68 from NC to TP Page25: delete R58 and add RN87 and change U5 to 72.24C02.R01 Page3: change R255 from 22R to 33R and change RN42 from 0ohm to 33R Page33: change R268 R275 R259 from 0ohm resistor to 0ohm pad Page35: change R394 from DY to mount and change R395 from mount to DY Page28: change R526 from 0ohm resistor to 0ohm pad Page35: change R401 from 0ohm resistor to 0ohm pad Page35: delete Q12 and add R502 R503 Page35: change RN23 pin from 3D3V_AUX_S5 to 3D3V_S0 C C Page44: change U46 to APL5930 by power team's request Page38: add 3G and BT option Page28: change R479 from 8K2 to 10K and change R480 from 6K2 to 4K99 for audio speaker gain Page28: merge CCD1 to LCD1 01/07 Page44: change R437 from 0ohm pad to 0ohm resistor Page9: change TC18 from UMA to DY and change C276 from DY to mount Page35: delete RN21 and add R507 10K DY Page38: change RN4 to 330R and change RN8 to 100R and delete R10 and change RN3 to 8P4R 200R Page47: change C515 to 78.15322.2FL by power team's request Page3: mount 33p on EC23 EC24 EC25 EC39 EC48 for RF's request Page3: add EC68 EC69 33p DY by RF's request Page20: add R129 4K7 for diffierent vendor B B 01/08 Page42: change R541 from 200K to 100K and change R544 location Page42: change R532 R545 from 0ohm pad to 0ohm resistor 01/09 Page38: Page50: Page50: Page50: change name from 3G/BT_LED1 to 3GBT_LED1 add SPRING_GND23 34.40U07.001, SPRING_GND24 34.40U07.001, SPRING_GND25 34.15J03.001 SPRING_GND17, SPRING_GND19 change from 34.41Y19.001 to 34.39S07.003 SPRING_GND18 change from 34.41Y19.001 to 34.4B312.002 A A JV50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title HISTORY Size A2 Document Number Date: Friday, January 09, 2009 Rev SB JV50 Sheet 61 of 60 ... K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD 11 BB 11 AY 11 AN 11 AH 11 Y 11 N 11 G 11 C 11 BG10 AV10 AT10 AJ10 AE10 AA10... A15 B15 C15 D15 E15 F15 L 11 L12 L14 L16 L17 L18 M 11 M18 P 11 P18 T 11 T18 U 11 U18 V 11 V12 V14 V16 V17 V18 SCD1U10V2KX-4GP AE1 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05... 58 68 70 12 9 13 1 14 1 14 3 13 0 13 2 14 0 14 2 14 7 14 9 15 7 15 9 14 6 14 8 15 8 16 0 16 3 16 5 17 5 17 7 16 4 16 6 17 4 17 6 18 1 18 3 19 1 19 3 18 0 18 2 19 2 19 4 BA0 BA1 11 4 12 1 SCD1U16V2ZY-2GP M_B_DQ0 M_B_DQ1 M_B_DQ2